M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 52

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Fig. 59 Structure of serial I/O1-related registers
7542 Group
Rev.3.03
REJ03B0006-0303
b7
b 7
Jul 11, 2008
b0
b 0
( S I O 1 S T S : a d d r e s s 0 0 1 9
S e r i a l I / O 1 s t a t u s r e g i s t e r
U A R T 1 c o n t r o l r e g i s t e r
( U A R T 1 C O N : a d d r e s s 0 0 1 B
T r a n s m i t b u f f e r e m p t y f l a g ( T B E )
0 : B u f f e r f u l l
1 : B u f f e r e m p t y
R e c e i v e b u f f e r f u l l f l a g ( R B F )
0 : B u f f e r e m p t y
1 : B u f f e r f u l l
T r a n s m i t s h i f t c o m p l e t i o n f l a g ( T S C )
0 : T r a n s m i t s h i f t i n p r o g r e s s
1 : T r a n s m i t s h i f t c o m p l e t e d
O v e r r u n e r r o r f l a g ( O E )
0 : N o e r r o r
1 : O v e r r u n e r r o r
P a r i t y e r r o r f l a g ( P E )
0 : N o e r r o r
1 : P a r i t y e r r o r
F r a m i n g e r r o r f l a g ( F E )
0 : N o e r r o r
1 : F r a m i n g e r r o r
S u m m i n g e r r o r f l a g ( S E )
0 : ( O E ) U ( P E ) U ( F E ) = 0
1 : ( O E ) U ( P E ) U ( F E ) = 1
N o t u s e d ( r e t u r n s “ 1 ” w h e n r e a d )
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P1
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
1
/T
X
D
1
P-channel output disable bit (POFF)
Page 50 of 117
1 6
, i n i t i a l v a l u e : 8 0
1 6
, i n i t i a l v a l u e : E 0
1 6
)
1 6
)
b 7
b 0
S e r i a l I / O 1 c o n t r o l r e g i s t e r
( S I O 1 C O N : a d d r e s s 0 0 1 A
B R G c o u n t s o u r c e s e l e c t i o n b i t ( C S S )
0 : f ( X
1 : f ( X
S e r i a l I / O 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( S C S )
0 : B R G o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s
1 : E x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l
S
0 : P 1
1 : P 1
T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( T I C )
0 : I n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d
1 : I n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d
T r a n s m i t e n a b l e b i t ( T E )
0 : T r a n s m i t d i s a b l e d
1 : T r a n s m i t e n a b l e d
R e c e i v e e n a b l e b i t ( R E )
0 : R e c e i v e d i s a b l e d
1 : R e c e i v e e n a b l e d
S e r i a l I / O 1 m o d e s e l e c t i o n b i t ( S I O M )
0 : C l o c k a s y n c h r o n o u s ( U A R T ) s e r i a l I / O
1 : C l o c k s y n c h r o n o u s s e r i a l I / O
S e r i a l I / O 1 e n a b l e b i t ( S I O E )
0 : S e r i a l I / O 1 d i s a b l e d
1 : S e r i a l I / O 1 e n a b l e d
R D Y 1
( p i n s P 1
( p i n s P 1
s e r i a l I / O i s s e l e c t e d , B R G o u t p u t d i v i d e d b y 1 6
w h e n U A R T i s s e l e c t e d .
I / O i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6
w h e n U A R T i s s e l e c t e d .
3
3
I N
I N
p i n o p e r a t e s a s o r d i n a r y I / O p i n
p i n o p e r a t e s a s S
o u t p u t e n a b l e b i t ( S R D Y )
)
) / 4
0
0
t o P 1
t o P 1
3
3
o p e r a t e a s s e r i a l I / O p i n s )
o p e r a t e a s o r d i n a r y I / O p i n s )
1 6
R D Y 1
, i n i t i a l v a l u e : 0 0
o u t p u t p i n
1 6
)