XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 86

• Manufacturer Part Number: XC68HC705B32CB
• Description: IC MCU 2.1MHZ 32K OTP 56-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6
6.11.3
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI
functions.
TIE — Transmit interrupt enable
TCIE — Transmit complete interrupt enable
RIE — Receiver interrupt enable
ILIE — Idle line interrupt enable
TE — Transmitter enable
When the transmit enable bit is set, the transmit shift register output is applied to the TDO line and
the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M
(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software
sets the TE bit from a cleared state.
If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the
present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high
impedance state.
If the TE bit has been written to a zero and then set to a one before the current byte is transmitted,
the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new
preamble. After this latest transmission, and provided the TDRE bit is set (no new data to
transmit), the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs.
This function allows the user to neatly terminate a transmission sequence.
Freescale
6-14
SCI control (SCCR2)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Serial communications control register 2 (SCCR2)
–
–
–
–
TDRE interrupts enabled.
TDRE interrupts disabled.
TC interrupts enabled.
TC interrupts disabled.
RDRF and OR interrupts enabled.
RDRF and OR interrupts disabled.
IDLE interrupts enabled.
IDLE interrupts disabled.
SERIAL COMMUNICATIONS INTERFACE
Address
$000F
bit 7
TIE
TCIE
bit 6
bit 5
RIE
bit 4
ILIE
bit 3
TE
bit 2
RE
RWU
bit 1
MC68HC05B6
bit 0
SBK
0000 0000
Rev. 4.1
on reset
State