XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 207

• Manufacturer Part Number: XC68HC705B32CB
• Description: IC MCU 2.1MHZ 32K OTP 56-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

E.4.4
The program first checks the state of the security bit. If the SEC bit is active, i.e. ‘0’, the program
will not enter the RAM bootstrap mode and the red LED will flash. Otherwise the RAM bootstrap
program will start loading the RAM with external data (e.g. from a 2564 or 2764 EPROM). Before
loading a new byte the state of the PD4/AN4 pin is checked. If this pin goes to level ‘0’, or if the
RAM is full, then control is given to the loaded program at address $0050. See
Figure
If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6
according to
disabled by connecting together PC5 and PC6.
Figure E-10
test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is
accomplished by means of the switches connected to the EPROM higher address lines (A8
through A10). If the user program sets PC0 to level ‘1’, this will disable the external EPROM, thus
rendering both port A output and port B input available. The EPROM parallel bootstrap loader
schematic can also be used
lines will be at zero. The LEDs will stay off.
MC68HC05B6
Rev. 4.1
E-4.
t
t
t
t
t
t
ADR
DHR
CR
HO
HI
EXR
max (PC6 handshake in, data hold time)
provides a schematic diagram of a circuit that can be used to load the RAM with short
(load cycle time; PC6=PC5)
(PC5 handshake out delay)
Figure
max (address to data delay; PC6=PC5)
min (data hold time)
max (max delay for transition to be recognised during this cycle; PC6=PC5
RAM parallel bootstrap
Address
PC5 out
PC6 in
Data
PD4
E-9. If the data comes from an external EPROM, the handshake can be
Figure E-9 Parallel RAM loader timing diagram
(Figure
t
HO
t
ADR
E-7), provided VPP is at V
1 machine cycle = 1/(2f
MC68HC705B16
t
EXR
t
t
max
HI
DHR
t
CR
max
0
(Xtal))
DD
level. The high order address
16 machine cycles
4 machine cycles
49 machine cycles
5 machine cycles
10 machine cycles
30 machine cycles
Figure E-3
Freescale
E-19
and
14