XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 114

• Manufacturer Part Number: XC68HC705B32CB
• Description: IC MCU 2.1MHZ 32K OTP 56-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9
9.2.3.3
There are five different timer interrupt flags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a
timer interrupt whenever they are set and enabled. These five interrupt flags are found in the five
most significant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will vector
to the service routine defined by $1FF8-$1FF9, OCF1 and OCF2 will vector to the service routine
defined by $1FF6–$1FF7 and TOF will vector to the service routine defined by $1FF4–$1FF5 as
shown in
There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2,
and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address
$0012. See
9.2.3.4
There are five different interrupt flags (TDRE, TC, OR, RDRF and IDLE) that cause SCI interrupts
whenever they are set and enabled. These five interrupt flags are found in the five most significant
bits of the SCI status register (SCSR) at location $0010.
There are four corresponding enable bits: TIE for TDRE, TCIE for TC, RIE for OR and RDRF, and
ILIE for IDLE. These enable bits are located in the serial communications control register 2
(SCCR2) at address $000F. See
The SCI interrupt causes the program counter to vector to the address pointed to by memory
locations $1FF2 and $1FF3 which contain the starting address of the interrupt service routine.
Software in the SCI interrupt service routine must determine the priority and cause of the interrupt
by examining the interrupt flags and the status bits located in the serial communications status
register SCSR (address $0010).
The general sequence for clearing an interrupt is a software sequence of accessing the serial
communications status register while the flag is set followed by a read or write of an associated
register. Refer to
Freescale
9-10
Figure
interrupt which is not latched); therefore, only one external interrupt pulse can be
latched during t
Section 5.2.1
Timer interrupts
Serial communications interface (SCI) interrupts
5.1.
Section 6
and
ILIL
for a description of the SCI system and its interrupts.
and serviced as soon as the I-bit is cleared.
Section 5.2.2
Section 6.11.3
RESETS AND INTERRUPTS
for further information.
and
Section
6.11.4.
MC68HC05B6
Rev. 4.1