C8051F020 Silicon Laboratories Inc, C8051F020 Datasheet - Page 91
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C8051F020
Manufacturer Part Number
C8051F020
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F020
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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9.
The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage reference
input pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage refer-
ence output. ADC0 may also reference the DAC0 output internally, and ADC1 may reference the analog power sup-
ply voltage, via the VREF multiplexers shown in Figure 9.1.
The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator
and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system
components or to the voltage reference input pins shown in Figure 9.1. Bypass capacitors of 0.1 µF and 4.7 µF are
recommended from the VREF pin to AGND, as shown in Figure 9.1. See Table 9.1 for voltage reference specifica-
tions.
The Reference Control Register, REF0CN (defined in Figure 9.2) enables/disables the internal reference generator
and selects the reference inputs for ADC0 and ADC1. The BIASE bit in REF0CN enables the on-board reference
generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled,
the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the
buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator,
BIASE and REFBE must both be set to logic 1. If the internal reference is not used, REFBE may be set to logic 0.
Note that the BIASE bit must be set to logic 1 if either DAC or ADC is used, regardless of whether the voltage refer-
ence is derived from the on-chip reference or supplied by an off-chip source. If neither the ADC nor the DAC are
being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD1VRS select the ADC0
and ADC1 voltage reference sources, respectively. The electrical specifications for the Voltage Reference circuit are
given in Table 9.1.
VOLTAGE REFERENCE (C8051F020/2)
Reference
External
Voltage
Circuit
Figure 9.1. Voltage Reference Functional Block Diagram
DGND
VDD
Recommended Bypass
4.7F
R1
Capacitors
0.1F
VREFD
VREF1
VREF0
VREF
Rev. 1.4
REF0CN
DAC0
DAC1
Ref
REFBE
x2
AV+
1
0
0
1
C8051F020/1/2/3
Band-Gap
BIASE
1.2V
EN
ADC1
ADC0
Ref
Ref
Bias to
ADCs,
DACs
91