C8051F020 Silicon Laboratories Inc, C8051F020 Datasheet - Page 102
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C8051F020
Manufacturer Part Number
C8051F020
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F020
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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C8051F020/1/2/3
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe-
cute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instruc-
tions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of
109 instructions. The table below shows the total number of instructions that require each execution time.
Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the FLASH program memory and commu-
nication with on-chip debug support logic. The re-programmable FLASH can also be read and changed a single byte
at a time by the application software using the MOVC and MOVX instructions. This feature allows program memory
to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware break-
points and watch points, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This
method of on-chip debug is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers, or other
on-chip resources.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an
integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via its JTAG interface to provide fast and efficient in-system
device programming and debugging. Third party macro assemblers and C compilers are also available.
12.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set;
standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the
binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on
PSW flags. However, instruction timing is different than that of the standard 8051.
12.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle tim-
ing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there
are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the
branch is not taken as opposed to when the branch is taken. Table 12.1 is the CIP-51 Instruction Set Summary, which
includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
12.1.2. MOVX Instruction and Program Memory
In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip XRAM,
and accessing on-chip program FLASH memory. The FLASH access feature provides a mechanism for user software
to update program code and use the program memory space for non-volatile data storage (see
102
Number of Instructions
Clocks to Execute
26
1
50
2
2/3
Rev. 1.4
5
14
3
3/4
7
4
3
4/5
1
Section “15. FLASH
5
2
8
1