C8051F020 Silicon Laboratories Inc, C8051F020 Datasheet - Page 205
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C8051F020
Manufacturer Part Number
C8051F020
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F020
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
C8051F020
Manufacturer:
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Silicon Laboratories Inc
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Part Number:
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20.
UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0 may operate
in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor communication is fully sup-
ported. Receive data is buffered in a holding register, allowing UART0 to start reception of a second incoming data
byte before software has finished reading the previous data byte. A Receive Overrun bit indicates when new received
data is latched into the receive buffer before the previous received byte is read.
UART0 is accessed via its associated SFRs, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The single
SBUF0 location provides access to both transmit and receive registers. Reads access the Receive register and writes
access the Transmit register automatically.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit Interrupt flag,
TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI0 (SCON0.0) set
when reception of a data byte is complete. UART0 interrupt flags are not cleared by hardware when the CPU vectors
to the interrupt service routine; they must be cleared manually by software. This allows software to determine the
cause of the UART0 interrupt (transmit complete or receive complete).
Generation
Baud Rate
UART0
UART
Logic
Write to
SBUF
Figure 20.1. UART0 Block Diagram
Tx Clock
Rx Clock
Start
Stop Bit
Start
Frame Error
Gen.
Detection
Load SBUF
D
TB8
SET
CLR
(Receive Latch)
Q
Shift
M
S
0
SFR Bus
M
S
1
SBUF
Tx Control
Rx Control
M
S
2
SCON
Shift
Input Shift Register
EN
(Transmit Shift)
R
E
N
Zero Detector
T
B
8
SFR Bus
SBUF
R
B
8
(9 bits)
Tx IRQ
T
I
Rx IRQ
SBUF
Read
R
I
0x1FF
Match Detect
Rev. 1.4
Address
TI
SBUF
Match
RI
Send
Load
Data
RB8
SADDR
SADEN
RX
TX
C8051F020/1/2/3
Crossbar
Crossbar
Serial Port
(UART0/1)
Interrupt
Port I/O
205