COP8SDE9IMT9/NOPB National Semiconductor, COP8SDE9IMT9/NOPB Datasheet - Page 15

• Manufacturer Part Number: COP8SDE9IMT9/NOPB
• Description: IC MCU EEPROM 8BIT 8K 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Sr

Specifications of COP8SDE9IMT9/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: *COP8SDE9IMT9; *COP8SDE9IMT9/NOPB; COP8SDE9IMT9

4.0 Functional Description
4.1 CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
S is the 8-bit Data Segment Address Register used to extend
the lower half of the address range (00 to 7F) into 256 data
segments of 128 bytes each.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). With reset the SP is initialized to
RAM address 06F Hex. The SP is decremented as items are
pushed onto the stack. SP points to the next available loca-
tion on the stack.
4.3 DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers and the USART (with the exception of the
IDLE timer). Data memory is addressed directly by the in-
struction or indirectly by the B, X and SP pointers.
The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, SP, B and S are memory mapped into this space
at address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumu-
lator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
4.4 DATA MEMORY SEGMENT RAM EXTENSION
Data memory address 0FF is used as a memory mapped
location for the Data Segment Address Register (S).
The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly rela-
tive to the reference of the B, X, or SP pointers (each
contains a single-byte address). This single-byte address
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
COP8SCE9
COP8SDE9
COP8SBE9
Device
Size (Flash)
Program
Memory
8192
C
) cycle time.
Flash Memory
TABLE 2. Available Memory Address Ranges
Page Size
(Bytes)
64
(Continued)
Option Register
Address (Hex)
1FFF
15
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
4.2 PROGRAM MEMORY
The program memory consists of 8192 bytes of Flash
Memory. These bytes may hold program instructions or con-
stant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS
instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 00FF Hex. The program memory
reads 00 Hex in the erased state. Program execution starts
at location 0 after RESET.
If a Return instruction is executed when the SP contains 6F
(hex), instruction execution will continue from Program
Memory location 7FFF (hex). If location 7FFF is accessed by
an instruction fetch, the Flash Memory will return a value of
00. This is the opcode for the INTR instruction and will cause
a Software Trap.
For the purpose of erasing and rewriting the Flash Memory,
it is organized in pages of 64 bytes as show in Table 2 .
allows an addressing range of 256 locations from 00 to FF
hex. The upper bit of this single-byte address divides the
data store memory into two separate sections as outlined
previously. With the exception of the RAM register memory
from address locations 00F0 – 00FF, all RAM memory is
memory mapped with the upper bit of the single-byte ad-
dress being equal to zero. This allows the upper bit of the
single-byte address to determine whether or not the base
address range (from 0000 – 00FF) is extended. If this upper
bit equals one (representing address range 0080 – 00FF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
register S is used to extend the base address range from
0000 – 007F to XX00 – XX7F, where XX represents the 8
bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 – 017F for data
segment 1, 0200 – 027F for data segment 2, etc., up to FF00
– FF7F for data segment 255. The base address range from
0000 – 007F represents data segment 0.
Refer to Table 2 , to determine available RAM segments for
this device.
Figure 7 illustrates how the S register data memory exten-
sion is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data seg-
ments of 128 bytes each with an additional upper base
segment of 128 bytes. Furthermore, all addressing modes
are available for all data segments. The S register must be
changed under program control to move from one data
segment (128 bytes) to another. However, the upper base
Data Memory
Size (RAM)
256
Segments
Available
0-1
Maximum
Address
(HEX)
www.national.com
RAM
017F