MC68HC16Z1CPV25 Freescale Semiconductor, MC68HC16Z1CPV25 Datasheet - Page 195

• Manufacturer Part Number: MC68HC16Z1CPV25
• Description: IC MPU 1K RAM 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CPV25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: Q1141110

M68HC16 Z SERIES
USER’S MANUAL
Mode 2 — A single conversion is performed on each of four sequential input channels,
starting with the channel specified by the value in CD:CA. Each result is stored in a
separate result register (RSLT0 to RSLT3). The appropriate CCF bit in ADCSTAT is
set as each register is filled. The SCF bit in ADCSTAT is set when the last conversion
is complete.
Mode 3 — A single conversion is performed on each of eight sequential input chan-
nels, starting with the channel specified by the value in CD:CA. Each result is stored
in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in ADCSTAT
is set as each register is filled. The SCF bit in ADCSTAT is set when the last conver-
sion is complete.
Mode 4 — Continuous four-conversion sequences are performed on a single input
channel specified by the value in CD:CA. Each result is stored in a separate result reg-
ister (RSLT0 to RSLT3). Previous results are overwritten when a sequence repeats.
The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in
ADCSTAT is set when the first four-conversion sequence is complete.
Mode 5 — Continuous eight-conversion sequences are performed on a single input
channel specified by the value in CD:CA. Each result is stored in a separate result reg-
ister (RSLT0 to RSLT7). Previous results are overwritten when a sequence repeats.
The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in
ADCSTAT is set when the first eight-conversion sequence is complete.
Mode 6 — Continuous conversions are performed on each of four sequential input
channels, starting with the channel specified by the value in CD:CA. Each result is
stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit in
ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the
first four-conversion sequence is complete.
Mode 7 — Continuous conversions are performed on each of eight sequential input
channels, starting with the channel specified by the value in CD:CA. Each result is
stored in a separate result register (RSLT0 to RSLT7). The appropriate CCF bit in
ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the
first eight-conversion sequence is complete.
Table 8-7
modes).
modes). Number of conversions per channel is determined by SCAN. Channel num-
bers are given in order of conversion.
Table 8-8
is a summary of ADC operation when MULT is cleared (single-channel
is a summary of ADC operation when MULT is set (multi-channel
Freescale Semiconductor, Inc.
For More Information On This Product,
ANALOG-TO-DIGITAL CONVERTER
Go to: www.freescale.com
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