MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 31

• Manufacturer Part Number: MC68HC11F1CFN4
• Description: IC MCU 512 EEPROM 4MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

3.1.6.8 Stop Disable (S)
3.2 Data Types
3.3 Opcodes and Operands
3.4 Addressing Modes
3.4.1 Immediate
TECHNICAL DATA
Setting the STOP disable (S) bit prevents the STOP instruction from putting the
M68HC11 into a low-power stop condition. If the CPU encounters a STOP instruction
while the S bit is set, it is treated as a no-operation (NOP) instruction, and processing
continues to the next instruction. S is set by reset — STOP disabled by default.
The M68HC11 CPU supports the following data types:
A byte is eight bits wide and can be accessed at any byte location. A word is composed
of two consecutive bytes with the most significant byte at the lower value address. Be-
cause the M68HC11 is an 8-bit CPU, there are no special requirements for alignment
of instructions or operands.
The M68HC11 family of microcontrollers uses 8-bit opcodes. Each opcode identifies
a particular instruction and associated addressing mode to the CPU. Several opcodes
are required to provide each instruction with a range of addressing capabilities. Only
256 opcodes would be available if the range of values were restricted to the number
able to be expressed in 8-bit binary numbers.
A four-page opcode map has been implemented to expand the number of instructions.
An additional byte, called a prebyte, directs the processor from page 0 of the opcode
map to one of the other three pages. As its name implies, the additional byte precedes
the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or
three operands. The operands contain information the CPU needs for executing the
instruction. Complete instructions can be from one to five bytes long.
Six addressing modes can be used to access memory: immediate, direct, extended,
indexed, inherent, and relative. These modes are detailed in the following paragraphs.
All modes except inherent mode use an effective address. The effective address is the
memory address from which the argument is fetched or stored, or the address from
which execution is to proceed. The effective address can be specified within an in-
struction, or it can be calculated.
In the immediate addressing mode an argument is contained in the byte(s) immediate-
ly following the opcode. The number of bytes following the opcode matches the size
of the register or memory location being operated on. There are two-, three-, and four-
• Bit data
• 8-bit and 16-bit signed and unsigned integers
• 16-bit unsigned fractions
• 16-bit addresses
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
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