MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 129

• Manufacturer Part Number: MC68HC11F1CFN4
• Description: IC MCU 512 EEPROM 4MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

10.2 A/D Converter Power-Up and Clock Select
OPTION — System Configuration Options
ADPU — A/D Power-Up
CSEL — Clock Select
IRQE — Configure IRQ for Edge-Sensitive Only Operation
DLY — Enable Oscillator Start-up Delay
CME — Clock Monitor Enable
FCME — Force Clock Monitor Enable
CR[1:0] — COP Timer Rate Select Bits
10.3 Conversion Process
TECHNICAL DATA
RESET:
Bit 7 of the OPTION register controls A/D converter power up. Clearing ADPU re-
moves power from and disables the A/D converter system. Setting ADPU enables the
A/D converter system. Stabilization of the analog bias voltages requires a delay of as
much as 100 s after turning on the A/D converter. When the A/D converter system is
operating with the MCU E clock, all switching and comparator operations are synchro-
nized to the MCU clocks. This allows the comparator results to be sampled at quiet
times, which minimizes noise errors. The internal RC oscillator is asynchronous to the
MCU clock, so noise affects A/D converter results, which lowers accuracy slightly
while CSEL = 1.
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes
Refer to SECTION 5 RESETS AND INTERRUPTS.
Refer to SECTION 5 RESETS AND INTERRUPTS.
Refer to SECTION 5 RESETS AND INTERRUPTS.
Refer to SECTION 5 RESETS AND INTERRUPTS.
Refer to SECTION 5 RESETS AND INTERRUPTS and SECTION 9 TIMING SYS-
TEM.
The A/D conversion sequence begins one E-clock cycle after a write to the A/D control/
status register, ADCTL. The bits in ADCTL select the channel and the mode of con-
version.
An input voltage equal to V
verts to $FF (full scale), with no overflow indication. For ratiometric conversions of this
type, the source of each analog input should use V
referenced to V
0 = A/D powered down
1 = A/D powered up
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock
ADPU
Bit 7
0
RL
CSEL
.
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
ANALOG-TO-DIGITAL CONVERTER
IRQE*
RL
5
0
Go to: www.freescale.com
converts to $00 and an input voltage equal to V
DLY*
4
1
CME
0
3
FCME*
RH
2
0
as the supply voltage and be
CR1*
1
0
CR0*
Bit 0
0
RH
$1039
con-
10-5