MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 28

• Manufacturer Part Number: MC68HC11F1CFN4
• Description: IC MCU 512 EEPROM 4MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

3-4
DIRECT
INDXD,X
INDXD,Y
RTS, RETURN FROM SUBROUTINE
JSR, JUMP TO SUBROUTINE
EXTEND
BSR, BRANCH TO SUBROUTINE
When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine
(BSR) instruction, the address of the instruction after the JSR or BSR is automatically
pushed onto the stack, least significant byte first. When the subroutine is finished, a
return from subroutine (RTS) instruction is executed. The RTS pulls the previously
stacked return address from the stack, and loads it into the program counter. Execu-
tion then continues at this recovered return address.
RTN
RTN
RTN
RTN
RTN
PC
PC
PC
PC
PC
PC
NEXT MAIN INSTR
NEXT MAIN INSTR
NEXT MAIN INSTR
NEXT MAIN INSTR
NEXT MAIN INSTR
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
SUBROUTINE
$8D = BSR
$9D = JSR
$AD = JSR
$18 = PRE
$AD = JSR
$BD = JSR
$39 = RTS
dd
hh
ff
ff
rr
ll
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 3-2 Stacking Operations
SP+2
CENTRAL PROCESSING UNIT
SP+1
SP-2
SP-2
SP-1
SP-1
SP
SP
SP
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STACK
STACK
STACK
RTN
RTN
RTN
RTN
RTN
RTN
H
H
H
L
L
L
RTI, RETURN FROM INTERRUPT
RTN
RTN
SWI, SOFTWARE INTERRUPT
WAI, WAIT FOR INTERRUPT
LEGEND:
PC
PC
PC
RTN
RTN
RTN
dd
hh
H
L
ff
rr
INTERRUPT PROGRAM
ll
MAIN PROGRAM
MAIN PROGRAM
Address of next instruction in main program to be
executed upon return from subroutine.
Most significant byte of return address.
Least significant byte of return address.
Shaded cells show stack pointer position after
operation is complete.
8-bit direct address ($0000-$00FF) (high byte
assumed to be $00).
8-bit positive offset $00 (0) to $FF (256) is added
to index.
High-order byte of 16-bit extended address.
Low-order byte of 16-bit extended address.
Signed-relative offset $80 (-128) to $7F (+127)
(offset relative to the address following the
machine code offset byte).
$3E = WAI
$3F = SWI
$3B = RTI
TECHNICAL DATA
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9
SP+1
SP-9
SP-8
SP-7
SP-6
SP-5
SP-4
SP-3
SP-2
SP-1
SP
SP
MC68HC11F1
INDEX REGISTER (X
INDEX REGISTER (Y
INDEX REGISTER (X
INDEX REGISTER (Y
INDEX REGISTER (X
INDEX REGISTER (Y
INDEX REGISTER (X
INDEX REGISTER (Y
CONDITION CODE
CONDITION CODE
ACMLTR B
ACMLTR A
ACMLTR B
ACMLTR A
STACK
STACK
RTN
RTN
RTN
RTN
H
H
L
L
H
H
H
H
L
L
L
L
)
)
)
)
)
)
)
)