MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 301

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

18.4.2 Breakpoint Registers
Breakpoint operation consists of comparing data in the breakpoint address registers (BRKAH/BRKAL) to
the address bus and comparing data in the breakpoint data registers (BRKDH/BRKDL) to the data bus.
The breakpoint data registers also can be compared to the address bus. The scope of comparison can
be expanded by ignoring the least significant byte of address or data matches.
The scope of comparison can be limited to program data only by setting the BKPM bit in breakpoint control
register 0.
To trace program flow, setting the BKPM bit causes address comparison of program data only. Control
bits are also available that allow checking read/write matches.
18.4.2.1 Breakpoint Control Register 0
Read and write anytime.
This register is used to control the breakpoint logic.
BKEN1 and BKEN0 — Breakpoint Mode Enable Bits
BKPM — Break on Program Addresses
BK1ALE — Breakpoint 1 Range Control Bit
Freescale Semiconductor
See
This bit controls whether the breakpoint causes an immediate data breakpoint (next instruction
boundary) or a delayed program breakpoint related to an executable opcode. Data and unexecuted
opcodes cannot cause a break if this bit is set. This bit has no meaning in SWI dual address mode.
The SWI mode only performs program breakpoints.
Only valid in dual address mode
BKEN1
0 = On match, break at the next instruction boundary
1 = On match, break if the match is an instruction to be executed. This uses tagging as its breakpoint
0 = BRKDL is not used to compare to the address bus.
1 = BRKDL is used to compare to the address bus.
Table
0
0
1
1
mechanism.
18-7.
Address: $0020
BKEN0
Reset:
Read:
Write:
0
1
0
1
BKEN1
Figure 18-10. Breakpoint Control Register 0 (BRKCT0)
Bit 7
Breakpoints off
SWI — dual address mode
BDM — full breakpoint mode
BDM — dual address mode
0
Mode Selected
BKEN0
Table 18-7. Breakpoint Mode Control
6
0
M68HC12B Family Data Sheet, Rev. 9.1
BKPM
5
0
4
0
0
Address match
Address match
Address match
BRKAH/L
Usage
BK1ALE
—
3
0
BK0ALE
2
0
Address match
Address match
Data match
BRKDH/L
Usage
—
1
0
0
R/W
Yes
Bit 0
Yes
No
—
0
0
Breakpoints
Range
Yes
Yes
Yes
—
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