MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 196

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Interface
RSRC — Receiver Source Bit
M — Mode Bit (select character format)
WAKE — Wakeup by Address Mark/Idle Bit
ILT — Idle Line Type Bit
PE — Parity Enable Bit
PT — Parity Type Bit
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When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver.
This bit determines which of two types of idle line detection is used by the SCI receiver.
In short mode, the SCI circuitry begins counting 1s in the search for the idle line condition immediately
after the start bit. This means that the stop bit and any bits that were 1s before the stop bit could be
counted in that string of 1s, resulting in earlier recognition of an idle line.
In long mode, the SCI circuitry does not begin counting 1s in the search for the idle line condition until
a stop bit is received. Therefore, the last byte’s stop bit and preceding 1 bits do not affect how quickly
an idle line condition can be detected.
If parity is enabled, this bit determines even or odd parity for both the receiver and the transmitter. An
even number of 1s in the data character causes the parity bit to be 0 and an odd number of 1s causes
the parity bit to be 1.
0 = Receiver input connected to the transmitter internally
1 = Receiver input connected to the TXD pin
0 = One start, eight data, one stop bit
1 = One start, eight data, ninth data, one stop bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (last data bit set)
0 = Short idle line mode enabled
1 = Long idle line mode detected
0 = Parity disabled
1 = Parity enabled
0 = Even parity selected
1 = Odd parity selected
(not TXD pin)
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor