MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 167

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MC68HC912B32CFU8

Manufacturer Part Number
MC68HC912B32CFU8
Description
IC MCU 32K FLASH 8MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC68HC912B32CFU8

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
768 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32CFU8
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC912B32CFU8
Manufacturer:
FREESCALE
Quantity:
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OC7M[7:0] Bits
13.4.4 Output Compare 7 Data Register
Read: Anytime
Write: Anytime
OC7D[7:0] Bits
Freescale Semiconductor
The bits of OC7M correspond bit-for-bit with the timer port (PORTT) bits. Setting the OC7Mn will set
the corresponding port to be an output port regardless of the state of the DDRTn bit, when the
corresponding TIOSn bit is set to be an output compare. This does not change the state of the DDRT
bits. At successful OC7, for each bit that is set in OC7M, the corresponding data bit OC7D is stored to
the corresponding bit of the timer port. See
The bits of OC7D correspond bit-for-bit with the bits of the timer port (PORTT). When a successful OC7
compare occurs, for each bit that is set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare action
during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit.
Address: $0083
OC7M has priority over output action on the timer port enabled by OMn and
OLn bits in TCTL1 and TCTL2. If an OC7M bit is set, it prevents the action
of corresponding OM and OL bits on the selected timer port.
Reset:
Read:
Write:
OC7D7
Figure 13-9. Output Compare 7 Data Register (OC7D)
Bit 7
0
with Output Compare/Pulse Accumulator A
OC7D6
Figure 13-8. Block Diagram for Port 7
OC7
6
0
M68HC12B Family Data Sheet, Rev. 9.1
PULSE ACCUMULATOR A
OM7 = 1 OR OL7 = 1 OR OC7M7 = 1
OC7D5
5
0
Figure
NOTE
OC7D4
4
0
13-8.
OC7D3
3
0
OC7D2
PAD
2
0
OC7D1
1
0
OC7D0
Bit 0
0
Timer Registers
167

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