STR750FV2H6 STMicroelectronics, STR750FV2H6 Datasheet - Page 66
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STR750FV2H6
Manufacturer Part Number
STR750FV2H6
Description
MCU 32BIT 256KB FLASH 100-LFBGA
Manufacturer
STMicroelectronics
Series
STR7r
Datasheet
1.STR750FV0T6.pdf
(84 pages)
Specifications of STR750FV2H6
Core Processor
ARM7
Core Size
32-Bit
Speed
60MHz
Connectivity
CAN, I²C, SPI, SSI, SSP, UART/USART, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
CAN, I2C, SPI, SSI, SSP, USB
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
72
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5988 - BOARD DEVELOPMENT LOVE STR750497-5754 - KIT STARTER IAR STR750497-5753 - KIT STARTER KEIL FOR STR7/STR9497-5752 - KIT STARTER IAR FOR STR7/STR9497-5751 - KIT STARTER HITEX FOR STR750497-5748 - BOARD EVALUATION FOR STR750XF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5649
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR750FV2H6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical parameters
66/84
Figure 34. SPI configuration - slave mode with CPHA=0, continuous transfer
Figure 35. SPI configuration, slave mode with CPHA=1, single transfer
Figure 36. SPI configuration - slave mode with CPHA=1, continuous transfer
MISO
MOSI
MISO
MOSI
MOSI
MISO
NSS
NSS
NSS
CPHA=1
CPOL=0
CPHA=1
CPOL=1
CPOL=0
OUTPUT
INPUT
CPOL=0
CPOL=1
CPOL=1
INPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
DONT CARE
DONT CARE
1 OR 0
1.5*t
t
NSSLQV
z
DONT CARE
c(SCK)
t
su(NSS)
z
t
NSSLQV
trigger
edge
trigger
MSB OUT
MSB IN
sample
MSB OUT
MSB IN
sample
t
t
w(SCKH)
w(SCKL)
trigger
MSB OUT
MSB IN
t
trigger
su(SI)
sample trigger
sample
sample
edge
t
t
FRAME 1
c(SCK)
h(SI)
trigger sample
FRAME 1
sample trigger
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
t
c(SCK)
t
t
trigger sample
SCKQV(MISO)
SCKQX(MISO)
samlpe trigger
t
c(SCK)
BIT OUT
trigger sample
LSB OUT
LSB IN
sample
LSB OUT
LSB IN
BIT1 IN
trigger
edge
trigger
MSB OUT
MSB IN
trigger
t
t
r(SCK)
f(SCK)
t
sample
NSHQZ
DONT CARE
1.5*t
FRAME 2
trigger
c(SCK)
sample
t
NSSLQV
LSB IN
edge
z
sample trigger
LSB OUT
MSB IN
MSB OUT
sample
t
h(NSS)
FRAME 2
sample trigger
trigger
t
t
sample
NSSHQX
NSSHQZ
DONT
CARE
z