STR750FV2H6 STMicroelectronics, STR750FV2H6 Datasheet - Page 48
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STR750FV2H6
Manufacturer Part Number
STR750FV2H6
Description
MCU 32BIT 256KB FLASH 100-LFBGA
Manufacturer
STMicroelectronics
Series
STR7r
Datasheet
1.STR750FV0T6.pdf
(84 pages)
Specifications of STR750FV2H6
Core Processor
ARM7
Core Size
32-Bit
Speed
60MHz
Connectivity
CAN, I²C, SPI, SSI, SSP, UART/USART, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
CAN, I2C, SPI, SSI, SSP, USB
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
72
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5988 - BOARD DEVELOPMENT LOVE STR750497-5754 - KIT STARTER IAR STR750497-5753 - KIT STARTER KEIL FOR STR7/STR9497-5752 - KIT STARTER IAR FOR STR7/STR9497-5751 - KIT STARTER HITEX FOR STR750497-5748 - BOARD EVALUATION FOR STR750XF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5649
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR750FV2H6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical parameters
48/84
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Figure 23. Self-referred jitter (single and long term)
Figure 24. Cycle-to-cycle jitter
difference between N+1 consecutive clock rising edges and T
difference between N+1 consecutive clock rising edges.
N should be kept sufficiently large to have a long term jitter (ex: thousands).
For N=1, this becomes the single period jitter.
See
Cycle-to-cycle jitter (N period jitter)
This corresponds to the time variation between adjacent cycles over a random sample
of adjacent clock cycles pairs. Jitter(cycle-to-cycle) = Max(Tcycle n- Tcycle n-1) for n=1
to N.
See
Figure 23
Figure 24
CK_PLL
ACTUAL
CK_PLL
IDEAL
CK_PLL
CK_PLL
ACTUAL
IDEAL
trigger point
n
n
T
T
Tcycle 1
single period
jitter
n+1
n+1
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Tcycle 2
n+2
---
---
long term
jitter
min
Tcycle N-1
n+N
is the minimum time
n+N