ST7FLITE39F2U6 STMicroelectronics, ST7FLITE39F2U6 Datasheet - Page 62
ST7FLITE39F2U6
Manufacturer Part Number
ST7FLITE39F2U6
Description
IC MCU 8BIT 8K FLASH 20QFN
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE35F2M6TR.pdf
(173 pages)
Specifications of ST7FLITE39F2U6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
For Use With
497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-6398 - BOARD EVAL ST7FLITE39/STM1403497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5514 - EVAL BOARD THERMO CONTROL REFRIG497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5635
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
11.2.3.2 Output Compare Mode
To use this function, load a 12-bit value in the
Preload DCRxH and DCRxL registers.
When the 12-bit upcounter (CNTR1) reaches the
value stored in the Active DCRxH and DCRxL reg-
isters, the CMPFx bit in the PWMxCSR register is
set and an interrupt request is generated if the
CMPIE bit is set.
The output compare function is always performed
on CNTR1 in both Single Timer mode and Dual
Timer mode, and never on CNTR2. The difference
is that in Single Timer mode the counter 1 can be
compared with any of the four DCR registers, and
Figure 41. Block Diagram of Output Compare Mode (single timer)
62/173
1
(ATCSR2)
(ATCSR)
TRAN1
OVF
DCRx
PRELOAD DUTY CYCLE REGx
ACTIVE DUTY CYCLE REGx
CNTR1
COUNTER 1
CMP
INTERRUPT
in Dual Timer mode, counter 1 is compared with
DCR0 or DCR1.
Notes:
1. The output compare function is only available
for DCRx values other than 0 (reset value).
2. Duty cycle registers are buffered internally. The
CPU writes in Preload Duty Cycle Registers and
these values are transferred in Active Duty Cycle
Registers after an overflow event if the corre-
sponding transfer bit (TRAN1 bit) is set. Output
compare is done by comparing these active DCRx
values with the counter.
OUTPUT COMPARE CIRCUIT
REQUEST
CMPIE
CMPFx (PWMxCSR)
(ATCSR)
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