ST7FLITE39F2U6 STMicroelectronics, ST7FLITE39F2U6 Datasheet - Page 130

• Manufacturer Part Number: ST7FLITE39F2U6
• Description: IC MCU 8BIT 8K FLASH 20QFN
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2U6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-6398 - BOARD EVAL ST7FLITE39/STM1403497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5514 - EVAL BOARD THERMO CONTROL REFRIG497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5635

ST7LITE3xF2
INSTRUCTION GROUPS (cont’d)
130/173
JRULE
LD
MUL
NEG
NOP
OR
POP
PUSH
RCF
RET
RIM
RLC
RRC
RSP
SBC
SCF
SIM
SLA
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
XOR
Mnemo
Jump if (C + Z = 1)
Load
Multiply
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
Disable Interrupts
Shift left Arithmetic
Shift right Logic
Shift right Arithmetic
Subtraction
SWAP nibbles
Test for Neg & Zero
S/W trap
Wait for Interrupt
Exclusive OR
Shift left Logic
Description
Unsigned <=
dst <= src
X,A = X * A
neg $10
A = A + M
pop reg
pop CC
push Y
C = 0
I = 0
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
I = 1
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
S/W interrupt
A = A XOR M
Function/Example
reg, M
A, X, Y
reg, M
A
reg
CC
M
reg, M
reg, M
A
reg, M
reg, M
reg, M
reg, M
A
A
Dst
M, reg
X, Y, A
M
M
M
reg, CC
M
M
M
Src
H
H
0
0
1
0
1
I
I
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
C
C
C
C
C
C
0
0
1