LH7A404N0F000B2 Sharp Microelectronics, LH7A404N0F000B2 Datasheet - Page 58

• Manufacturer Part Number: LH7A404N0F000B2
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2468; LH7A404N0F000B2

LH7A404
58
6/10/04
1/14/05
4/1/04
9/1/04
DATE
1, 30, 31
Various
Various
Various
38 - 41
PAGE
14-16
4-12
NO.
ALL
13
21
34
36
37
54
30
53
29
55
31
31
36
1
4
1
Text
Text
Table 1
Table 3
Pin List
Table 5
Table 6
Table 7
Table 9
Table 9
Text
1.8 VDC Tolerance
Text
Table 1
Power Sequencing
Text
Note to Table
Figure 37, Table 12
Text
Text
“5 V Tolerant” bullet
DC Specifications
Power Sequencing
Table 11
Figure 8 - Figure 11
PARAGRAPH OR
ILLUSTRATION
Table 13. Record of Revisions
Clarified Industrial and Commercial temperature ranges; removed MMC/SD as
a boot device.
Removed 1.8 VDC I/O capability (VDD).
Changed “BOOTWIDTH” to “WIDTH” for consistency.
Extensively revised to make more usable.
Minor corrections to Slew Rate and Output Drive on some cells.
Revised Boot Mode table to show various device possibilities.
External Boot Modes table Added.
Changed ‘MAXIMUM’ test conditions from maximum temperature to nominal
temperature.
Changed Synchronous Memory Interface tISD to 2.5 ns.
Changed MMC timing reference to ‘MMC Clock Periods’; minor changes to
several timing values; changed ADC resolution value.
Altered low pass filter description.
Changed 1.8 VDC supply voltage to ±5%.
Minor text editing for clarity.
Minor editorial corrections.
Paragraph added explaining sequencing of power supplies.
Added ground connection to drawing and removed the “Caution” box.
Clarified Note 1.
Temperature/Voltage/Speed chart and Table added.
Rolled revision to Version 1.0.
Cleaned up formatting.
Added sub-bullet limiting voltage on the oscillator pins.
Added “Typ.” column and corrected values for IACTIVE, IHALT, ISTANDBY.
Added text to allow power up sequencing longer than 100
within 1.5 V.
Changed Asynchronous Memory timing to match SRAM datasheet parameter
naming conventions. Corrected Asynchronous Memory values for tOHCA,
tOHRA, tOHSDW, tOHSC, and tOHD; added value for tOHA. Corrected
PCMCIA D[31:0] timing values tISD and tIHD.
Revised drawings to match SRAM datasheet parameter naming conventions.
Version 1.0
SUMMARY OF CHANGES
32-Bit System-on-Chip
µs
if supplies remain
Data Sheet