LH7A404N0F000B2 Sharp Microelectronics, LH7A404N0F000B2 Datasheet - Page 21

• Manufacturer Part Number: LH7A404N0F000B2
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2468; LH7A404N0F000B2

32-Bit System-on-Chip
Vectored Interrupt Controller (VIC)
manage interrupt requests from on-chip and off-chip
sources. Each VIC performs these primary functions:
• Determine if an interrupt source is disabled or can
• Prioritize up to 16 separate interrupt sources for
• Obtain the address of the interrupt handler (vector)
• Provide a default vector and a set of status registers
to 64 different interrupts, 32 of which are vectored. The
VIC supports both FIQ and IRQ interrupts. FIQ inter-
Data Sheet
8-bit ROM
16-bit ROM
32-bit ROM
Invalid: Do not allow this condition.
16-bit SynchFlash (Initializes device MODE Register)
16-bit SROM (Initializes device MODE Register)
32-bit SynchFlash (Initializes device MODE Register)
32-bit SROM (Initializes device MODE Register)
Boot from internal Boot ROM; see Table 5
External device
8-bit interface, 3-byte address NAND Flash
8-bit interface, 4-byte address NAND Flash
8-bit interface, 5-byte address NAND Flash
16-bit interface, 3-byte address NAND Flash
16-bit interface, 4-byte address NAND Flash
16-bit interface, 5-byte address NAND Flash
XMODEM using UART2
I
Undefined
2
C EEPROM
generate an FIQ or IRQ to the ARM core
simultaneous and nested processing
for up to 16 interrupt sources
for up to 16 non-vectored sources. Software deter-
mines the priority of these interrupts.
The LH7A404 has two VICs working together to
Two VICs are daisy-chained together to support up
BOOT DEVICE
BOOT MODE
Table 6. External Boot Modes
Table 5. Internal Boot Modes
GPIO
PA7
0
0
0
1
1
1
0
0
0
0
1
1
Version 1.0
LATCHED
MEDCHG
0
0
0
0
0
0
1
1
0
1
0
1
rupts have a higher priority than IRQ interrupts. If two
interrupts with the same priority become active at the
same time, the priority must be resolved in software.
When an interrupt becomes active, the VIC generates
an FIQ or IRQ if the corresponding mask bit is set.
Interrupts are not latched in the VIC, but may latch on
a particular peripheral when applicable.
cleared, masking all interrupts. They must be set by
software after power-on reset to enable interrupts.
vides direct information about where its service routine
is located and eliminates software arbitration needed
with a simple interrupt controller.
modes, so external interrupts may bring the chip out of
these low power modes.
WIDTH1
After a power-on reset, all mask register bits are
A vectored interrupt has improved latency as it pro-
The VICs continue to operate in Halt and Standby
0
0
1
1
0
0
1
1
x
See Table 6
LATCHED
WIDTH1
0
0
1
0
0
1
0
0
1
1
1
x
WIDTH0
0
1
0
1
0
1
0
1
x
LATCHED
WIDTH0
MEDCHG
0
1
0
0
1
0
0
1
1
1
1
x
0
0
0
0
1
1
1
1
x
LATCHED
INTBOOT
INTBOOT
LH7A404
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
21