ADUC812BS Analog Devices Inc, ADUC812BS Datasheet - Page 9

IC ADC 12BIT MULTICH MCU 52-MQFP

ADUC812BS

Manufacturer Part Number
ADUC812BS
Description
IC ADC 12BIT MULTICH MCU 52-MQFP
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC812BS

Rohs Status
RoHS non-compliant
Core Processor
8052
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-MQFP, 52-PQFP

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REV. E
ARCHITECTURE, MAIN FEATURES
The ADuC812 is a highly integrated, true 12-bit data acquisi-
tion system. At its core, the ADuC812 incorporates a high
performance 8-bit (8052 compatible) MCU with on-chip
reprogrammable nonvolatile Flash program memory control-
ling a multichannel (eight input channels) 12-bit ADC.
The chip incorporates all secondary functions to fully support
the programmable data acquisition core. These secondary
functions include User Flash Memory, Watchdog Timer
(WDT), Power Supply Monitor (PSM), and various industry-
standard parallel and serial interfaces.
The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
16 bytes (128 bits) above the register banks form a block of
bit addressable memory space at bit addresses 00H through 7FH.
00H
9FH
LOWER
UPPER
128
128
Figure 1. Program and Data Memory Maps
CONTROL REGISTERS
FFH
7FH
80H
00H
FLASH/EE DATA
INDIRECTLY
ACCESSED
640 BYTES
(PAGE 159)
DATA MEMORY
MEMORY
(PAGE 0)
ADDRESSING
ADDRESSING
VIA SFR
ACCESSIBLE
ACCESSIBLE
INTERNAL
INDIRECT
INDIRECT
PROGRAM
INTERNAL
FLASH/EE
MEMORY
DIRECT
8K BYTE
SPACE
ONLY
EA = 1
AND
BY
BY
FFFFH
2000H
PROGRAM MEMORY SPACE
DATA MEMORY SPACE
ADDRESSING
ACCESSIBLE
REGISTERS
EXTERNAL
PROGRAM
BY DIRECT
READ ONLY
FUNCTION
MEMORY
READ/WRITE
SPECIAL
SPACE
1FFFH
0000H
ONLY
EXTERNAL
PROGRAM
FFH
MEMORY
80H
SPACE
EA = 0
FFFFFFH
000000H
EXTERNAL
ADDRESS
MEMORY
SPACE)
SPACE
(24-BIT
DATA
–9–
MEMORY ORGANIZATION
As with all 8052 compatible devices, the ADuC812 has separate
address spaces for program and data memory as shown in Fig-
ure 1. Also as shown in Figure 1, an additional 640 bytes of
User Data Flash EEPROM are available to the user. The User
Data Flash Memory area is accessed indirectly via a group of
control registers mapped in the Special Function Register (SFR)
area in the Data Memory Space.
The SFR space is mapped in the upper 128 bytes of internal data
memory space. The SFR area is accessed by direct addressing
only and provides an interface between the CPU and all on-chip
peripherals. A block diagram showing the programming model
of the ADuC812 via the SFR area is shown in Figure 3.
BITS IN PSW
SELECTED
BANKS
FLASH/EE PROGRAM
REPROGRAMMABLE
VIA
ELECTRICALLY
NONVOLATILE
COMPATIBLE
Figure 2. Lower 128 Bytes of Internal RAM
MEMORY
8K BYTE
CORE
8051
11
10
01
00
Figure 3. Programming Model
20H
18H
10H
08H
00H
FUNCTION
REGISTER
128-BYTE
SPECIAL
AREA
2FH
1FH
0FH
7FH
17H
07H
(BIT ADDRESSES 0FH–7FH)
4 BANKS OF 8 REGISTERS
BIT ADDRESSABLE SPACE
RESET VALUE OF
STACK POINTER
REPROGRAMMABLE
AUTOCALIBRATING
ADuC812
OTHER ON-CHIP
2
FLASH/EE DATA
TEMPERATURE
ELECTRICALLY
PERIPHERALS
NONVOLATILE
PARALLEL I/O
HIGH SPEED
8-CHANNEL
SERIAL I/O
12-BIT ADC
R0–R7
640-BYTE
MEMORY
SENSOR
12-BIT DACs
WDT
PSM

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