ADUC812BS Analog Devices Inc, ADUC812BS Datasheet - Page 36

• Manufacturer Part Number: ADUC812BS
• Description: IC ADC 12BIT MULTICH MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC812BS

• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP

ADuC812
Mode 0 (8-Bit Shift Register Mode)
Mode 0 is selected by clearing both the SM0 and SM1 bits in the
SFR SCON. Serial data enters and exits through RxD. TxD
outputs the shift clock. Eight data bits are transmitted or received.
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RxD line. The eight bits are
transmitted with the least significant bit (LSB) first, as shown
in Figure 32.
Reception is initiated when the receive enable bit (REN) is 1 and
the receive interrupt bit (RI) is 0. When RI is cleared, the data
is clocked into the RxD line and the clock pulses are output
from the TxD line.
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore 10 bits are transmitted on TxD or received
on RxD. The baud rate is set by the Timer 1 or Timer 2 overflow
rate, or a combination of the two (one for transmission and the
other for reception).
Transmission is initiated by writing to SBUF. The “write to SBUF”
signal also loads a 1 (stop bit) into the ninth bit position of the
transmit shift register. The data is output bit by bit until the stop
bit appears on TxD and the transmit interrupt flag (TI) is auto-
matically set, as shown in Figure 33.
Reception is initiated when a 1-to-0 transition is detected on
RxD. Assuming a valid start bit was detected, character reception
continues. The start bit is skipped and the eight data bits are
clocked into the serial port shift register. When all eight bits have
been clocked in, the following events occur:
This will be the case if, and only if, the following conditions are
met at the time the final shift pulse is generated:
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
(SCON.1)
(DATA OUT)
The eight bits in the receive shift register are latched into SBUF.
The ninth bit (Stop bit) is clocked into RB8 in SCON.
The Receiver interrupt flag (RI) is set.
RI = 0, and
Either SM2 = 0 or SM2 = 1 and the received stop bit = 1.
CLOCK)
TxD
Figure 32. UART Serial Port Transmission, Mode 0
Figure 33. UART Serial Port Transmission, Mode 0
(SHIFT
CORE
TI
CLK
ALE
RxD
TxD
START
BIT
S1
S2
D0
DATA BIT 0
MACHINE
CYCLE 1
S3
S4
D1
S5
S6
D2
S1
DATA BIT 1
D3
S2
MACHINE
CYCLE 2
S3
D4
S4
D5
MACHINE
CYCLE 7
DATA BIT 6
S4
i.e., READY FOR MORE DATA
D6
S5
S6
SET INTERRUPT
D7
S1
S2
DATA BIT 7
MACHINE
STOP BIT
CYCLE 8
S3
S4
S5
S6
–36–
Mode 2 (9-Bit UART with Fixed Baud Rate)
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_Clk/64 by default, although by
setting the SMOD bit in PCON, the frequency can be doubled to
Core_Clk/32. Eleven bits are transmitted or received, a start
bit (0), eight data bits, a programmable ninth bit, and a stop bit
(1). The ninth bit is most often used as a parity bit, although it
can be used for anything, including a ninth data bit if required.
To transmit, the eight data bits must be written into SBUF. The
ninth bit must be written to TB8 in SCON. When transmission is
initiated, the eight data bits (from SBUF) are loaded onto the
transmit shift register (LSB first). The contents of TB8 are loaded
into the ninth bit position of the transmit shift register. The trans-
mission will start at the next valid baud rate clock. The TI flag
is set as soon as the stop bit appears on TxD.
Reception for Mode 2 is similar to that of Mode 1. The eight
data bytes are input at RxD (LSB first) and loaded onto the
receive shift register. When all eight bits have been clocked in,
the following events occur:
This will be the case if, and only if, the following conditions are
met at the time the final shift pulse is generated:
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 3 (9-Bit UART with Variable Baud Rate)
Mode 3 is selected by setting both SM0 and SM1. In this mode
the 8051 UART serial port operates in 9-bit mode with a variable
baud rate determined by either Timer 1 or Timer 2. The opera-
tion of the 9-bit UART is the same as for Mode 2, but the baud
rate can be varied as for Mode 1.
In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is initiated in
Mode 0 by the condition RI = 0 and REN = 1. Reception is
initiated in the other modes by the incoming start bit if REN = 1.
UART Serial Port Baud Rate Generation
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed:
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the SMOD bit
in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core
clock. If SMOD = 1, the baud rate is 1/32 of the core clock:
Mode 1 and 3 Baud Rate Generation
The baud rates in Modes 1 and 3 are determined by the overflow
rate in Timer 1 or Timer 2, or both (one for transmit and the
other for receive).
The eight bits in the receive shift register are latched into SBUF.
The ninth data bit is latched into RB8 in SCON.
The Receiver interrupt flag (RI) is set.
RI = 0, and
Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.
Mode
Mode
2
Baud Rate
0
Baud Rate
=
(
2
SMOD
=
(
Core Clock Frequency
64
)
×
(
Core Clock Frequency
12
)
REV. E
)