ADUC812BS Analog Devices Inc, ADUC812BS Datasheet - Page 16

• Manufacturer Part Number: ADUC812BS
• Description: IC ADC 12BIT MULTICH MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC812BS

• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP

ADuC812
However, be sure to include the Schottky diodes shown in
Figure 8 (or at least the lower of the two diodes) to protect the
analog input from undervoltage conditions. To summarize this
section, use the circuit of Figure 8 to drive the analog input pins
of the ADuC812.
Voltage Reference Connections
The on-chip 2.5 V band gap voltage reference can be used as
the reference source for the ADC and DACs. To ensure the
accuracy of the voltage reference, decouple both the V
the C
shown in Figure 9.
The internal voltage reference can also be tapped directly from
the V
buffer must be used to ensure that no current is drawn from the
V
node within the buffer block, and its voltage is critical to ADC
and DAC accuracy. Do not connect anything to this pin except
the capacitor, and be sure to keep trace-lengths short on the
C
ground plane.
The ADuC812 powers up with its internal voltage reference in the
“off” state. The voltage reference turns on automatically whenever
the ADC or either DAC gets enabled in software. Once enabled,
the voltage reference requires approximately 65 ms to power up
and settle to its specified value. Be sure that your software allows
this time to elapse before initiating any conversions. If an external
voltage reference is preferred, connect it to the V
in Figure 10 to overdrive the internal reference.
To ensure accurate ADC operation, the voltage applied to V
must be between 2.3 V and AV
input signals are proportional to the power supply (such as some
strain gage applications), it may be desirable to connect the
V
must also connect the C
internal buffer headroom limitations. This allows the ADC
input transfer function to span the full range of 0 V to AV
accurately.
Operation of the ADC or DACs with a reference voltage below
2.3 V, however, may incur loss of accuracy resulting in missing
codes or nonmonotonicity. For that reason, do not use a reference
voltage less than 2.3 V.
REF
REF
REF
REF
REF
pin itself. The voltage on the C
pin directly to AV
capacitor, decoupling the node straight to the underlying
pin to ground with 0.1 µF ceramic chip capacitors as
pin, if desired, to drive external circuitry. However, a
BUFFER
0.1 F
0.1 F
Figure 9. Decoupling V
C
V
REF
REF
DD
REF
. In such a configuration, the user
pin directly to AV
BUFFER
51
DD
. In situations where analog
ADuC812
REF
REF
REFERENCE
pin is that of an internal
BAND GAP
and C
2.5V
DD
REF
REF
to circumvent
pin as shown
REF
pin and
DD
REF
–16–
Configuring the ADC
The three SFRs (ADCCON1, ADCCON2, ADCCON3) con-
figure the ADC. In nearly all cases, an acquisition time of one
ADC clock (ADCCON1.2 = 0, ADCCON1.3 = 0) will provide
plenty of time for the ADuC812 to acquire its signal before
switching the internal track-and-hold amplifier into hold mode.
The only exception would be a high source impedance analog
input, but these should be buffered first anyway since source
impedances of greater than 610 Ω can cause dc errors as well.
The ADuC812’s successive approximation ADC is driven by a
divided down version of the master clock. To ensure adequate
ADC operation, this ADC clock must be between 400 kHz and
4 MHz, and optimum performance is obtained with ADC clock
between 400 kHz and 3 MHz. Frequencies within this range can
be achieved with master clock frequencies from 400 kHz to well
above 16 MHz with the four ADC clock divide ratios to choose
from. For example, with a 12 MHz master clock, set the ADC
clock divide ratio to 4 (i.e., ADCCLK = MCLK/4 = 3 MHz) by
setting the appropriate bits in ADCCON1 (ADCCON1.5 = 1,
ADCCON1.4 = 0).
The total ADC conversion time is 15 ADC clocks, plus one
ADC clock for synchronization, plus the selected acquisition
time (1, 2, 3, or 4 ADC clocks). For the example above, with a
one clock acquisition time, total conversion time is 17 ADC clocks
(or 5.67 µs for a 3 MHz ADC clock).
In continuous conversion mode, a new conversion begins each
time the previous one finishes. The sample rate is the inverse of the
total conversion time described above. In the example above, the
continuous conversion mode sample rate would be 176.5 kHz.
ADC DMA Mode
The on-chip ADC has been designed to run at a maximum
conversion speed of 5 µs (200 kHz sampling rate). When con-
verting at this rate, the ADuC812 MicroConverter has 5 µs to
read the ADC result and store the result in memory for further
postprocessing, otherwise the next ADC sample could be lost.
In an interrupt driven routine, the MicroConverter would also
have to jump to the ADC Interrupt Service routine, which will
also increase the time required to store the ADC results. In
applications where the ADuC812 cannot sustain the interrupt
rate, an ADC DMA mode is provided.
To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set.
This allows the ADC results to be written directly to a 16 MByte
external static memory SRAM (mapped into data memory space)
Figure 10. Using an External Voltage Reference
REFERENCE
EXTERNAL
VOLTAGE
V
DD
0.1 F
0.1 F
V
C
REF
REF
BUFFER
51
ADuC812
REFERENCE
BAND GAP
2.5V
REV. E