AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 394
![IC ARM7 MCU FLASH 256K 128-LQFP](/photos/6/71/67112/128-lqfp_sml.jpg)
AT91SAM7SE256-AU
Manufacturer Part Number
AT91SAM7SE256-AU
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT88SC-SDK1.pdf
(90 pages)
2.AT91SAM7SE256-AU.pdf
(673 pages)
3.AT91SAM7SE32-AU.pdf
(655 pages)
Specifications of AT91SAM7SE256-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
88
Number Of Timers
2
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
88
Ram Memory Size
32KB
Cpu Speed
48MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE256-AU
Manufacturer:
ATMEL
Quantity:
165
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33.9.7
33.9.7.1
Figure 33-22. Repeated Start + Reversal from Read to Write Mode
Note:
33.9.7.2
Figure 33-23. Repeated Start + Reversal from Write to Read Mode
Notes:
394
TWI_RHR
TWI_RHR
TWI_THR
TWI_THR
TXCOMP
EOSACC
TXCOMP
SVREAD
EOSACC
SVREAD
RXRDY
RXRDY
SVACC
SVACC
TXRDY
TXRDY
TWD
TWD
1. 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
AT91SAM7SE512/256/32 Preliminary
Reversal after a Repeated Start
the ACK.
Reversal of Read to Write
Reversal of Write to Read
S
S
As soon as a START is detected
As soon as a START is detected
SADR
SADR
The master initiates the communication by a read command and finishes it by a write command.
Figure 33-22
The master initiates the communication by a write command and finishes it by a read command.
Figure 33-23
W
R
Read TWI_RHR
A
A
DATA0
DATA0
DATA0
describes the repeated start + reversal from Read to Write mode.
describes the repeated start + reversal from Write to Read mode.
A
A
DATA0
DATA1
DATA1
DATA1
NA
A
DATA1
RS
RS
SADR
SADR
Cleared after read
Cleared after read
W
R
DATA2
A
A
DATA2
DATA2
DATA2
A
A
DATA3
DATA3
DATA3
6222B–ATARM–26-Mar-07
DATA3
NA
A
P
P
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