AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 392

• Manufacturer Part Number: AT91SAM7SE256-AU
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 88
• Ram Memory Size: 32KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

33.9.6
33.9.6.1
Figure 33-20. Clock Synchronization in Read Mode
Notes:
392
TWI_THR
TXCOMP
SVREAD
SCLWS
SVACC
TXRDY
TWCK
1. TXRDY is reset when data has been written in theTWI_TH to the shift register and set when this data has been acknowl-
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
3. SCLWS is automatically set when the clock synchronization mechanism is started.
AT91SAM7SE512/256/32 Preliminary
Clock Synchronization
edged or non acknowledged.
SADR.
Clock Synchronization in Read Mode
1
2
S
S
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
As soon as a START is detected
SADR
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emp-
tied before the emission/reception of a new character. In this case, to avoid sending/receiving
undesired data, a clock stretching mechanism is implemented.
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition
was not detected. It is tied low until the shift register is loaded.
Figure 33-20
DATA0
DATA0
R
Write THR
A
1
describes the clock synchronization in Read mode.
DATA0
A
DATA1
DATA1
CLOCK is tied low by the TWI
as long as THR is empty
A
XXXXXXX
2
DATA2
DATA2
Ack or Nack from the master
NA
S
6222B–ATARM–26-Mar-07