AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet - Page 67

• Manufacturer Part Number: AT80C51SND1C-ROTUL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.4
13.5
13.6
13.6.1
4109L–8051–02/08
Frame Information
Ancillary Data
Interrupt
Description
The MP3 frame header contains information on the audio data contained in the frame. These
informations is made available in the MP3STA register for you information. MPVER and
MPFS1:0 bits allow decoding of the sampling frequency according to Table 72. MPVER bit gives
the MPEG version (2 or 1).
Table 72. MP3 Frame Frequency Sampling
MP3 frames also contain data bits called ancillary data. These data are made available in the
MP3ANC register for each frame. As shown in Figure 13-4, the ancillary data are available by
Bytes when MPANC flag in MP3STA register is set. MPANC flag is set when the ancillary buffer
is not empty (at least one ancillary data is available) and is cleared only when there is no more
ancillary data in the buffer. This flag can generate an interrupt as explained in Section "Inter-
rupt", page 67. When set, software must read all Bytes to empty the ancillary buffer.
Figure 13-4. Ancillary Data Block Diagram
As shown in Figure 13-5, the MP3 decoder implements five interrupt sources reported in ERR-
CRC, ERRSYN, ERRLAY, MPREQ, and MPANC flags in MP3STA register.
All these sources are maskable separately using MSKCRC, MSKSYN, MSKLAY, MSKREQ, and
MSKANC mask bits respectively in MP3CON register.
The MP3 interrupt is enabled by setting EMP3 bit in IEN0 register. This assumes interrupts are
globally enabled by setting EA bit in IEN0 register.
All interrupt flags but MPREQ and MPANC are cleared when reading MP3STA register. The
MPREQ flag is cleared by hardware when no more data is requested (see Figure 13-2) and
MPANC flag is cleared by hardware when the ancillary buffer becomes empty.
Data To C51
Ancillary
MPVER
0
0
0
0
1
1
1
1
8
MPFS1
0
0
1
1
0
0
1
1
MP3ANC
MPFS0
8
0
1
0
1
0
1
0
1
Ancillary Buffer
7-Byte
Fs (kHz)
22.05 (MPEG II)
24 (MPEG II)
16 (MPEG II)
Reserved
44.1 (MPEG I)
48 (MPEG I)
32 (MPEG I)
Reserved
AT8xC51SND1C
MP3STA.7
MPANC
67