AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet - Page 105

• Manufacturer Part Number: AT80C51SND1C-ROTUL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4109L–8051–02/08
Reset Value = 0000 0000b
Table 99. UEPIEN Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
Reset Value = 0000 0000b
Table 100. UEPINT Register
UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register
Number
Number
7 - 3
7 - 3
Bit
Bit
2
1
0
7
2
1
0
7
-
-
Mnemonic Description
Mnemonic Description
EP2INTE
EP1INTE
EP0INTE
EP2RST
EP1RST
EP0RST
Bit
Bit
6
6
-
-
-
-
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 FIFO Reset
Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 1 FIFO Reset
Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 0 FIFO Reset
Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 Interrupt Enable Bit
Set to enable the interrupts for endpoint 2.
Clear this bit to disable the interrupts for endpoint 2.
Endpoint 1 Interrupt Enable Bit
Set to enable the interrupts for the endpoint 1.
Clear to disable the interrupts for the endpoint 1.
Endpoint 0 Interrupt Enable Bit
Set to enable the interrupts for the endpoint 0.
Clear to disable the interrupts for the endpoint 0.
5
5
-
-
4
4
-
-
3
3
-
-
EP2INTE
AT8xC51SND1C
EP2INT
2
2
EP1INTE
EP1INT
1
1
EP0INTE
EP0INT
0
0
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