ACE1001MT8X Fairchild Semiconductor, ACE1001MT8X Datasheet - Page 28

• Manufacturer Part Number: ACE1001MT8X
• Description: IC MCU 1KBIT EEPROM 8TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: ACEX® 10xxr

Specifications of ACE1001MT8X

• Core Processor: ACE1001
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

ACE1001 Product Family Rev. B.1
Figure 26: Crystal 9 (a) and RC (b) Oscillator Diagrams
15.0 HALT Mode
The HALT mode is a power saving feature that almost completely
shuts down the device for current conservation. The device is
placed into HALT mode by setting the HALT enable bit (EHALT)
of the HALT register through software using only the “LD M, #”
instruction. EHALT is a write only bit and is automatically cleared
upon exiting HALT. When entering HALT, the internal oscillator
and all the on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit HALT mode only by the MIW circuit. There-
fore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 8.0) After a wakeup from
HALT, a 64 clock cycle start-up delay is initiated to allow the
internal oscillator to stabilize before normal execution resumes.
Immediately after exiting HALT, software must clear the Power
Mode Clear (PMC) register by only using the “LD M, #” instruction.
(See Figure 28)
Figure 27: HALT Register Definition
Figure 28: Recommended HALT Flow
Bit 7
x
Multi-Input
Wakeup
Bit 6
x
LD HALT, #01h
LD PMC, #00h
Normal Mode
Normal Mode
Resume
Halt
33pF
a)
Bit 5
(G1)
CKI
x
1M
CKO
(G0)
33pF
Bit 4
x
28
b)
16.0 IDLE Mode
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed into
IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT
register through software using only the “LD M, #” instruction.
EIDLE is a write only bit and is automatically cleared upon exiting
IDLE. The IDLE mode operation is similar to HALT except the
internal oscillator, the Watchdog, and the Timer 0 remain active
while the other on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit IDLE by a Timer 0 overflow every 8192 cycles
or/and by the MIW circuit. If exiting IDLE mode with the MIW, prior
to entering, software must configure the MIW circuit accordingly.
(See Section 8.0) Once a wake from IDLE mode is triggered, the
core will begin normal operation by the next clock cycle. Immedi-
ately after exiting IDLE mode, software must clear the Power
Mode Clear (PMC) register by using only the “LD M, #” instruction.
(See Figure 29)
Figure 29: Recommended IDLE Flow
C
Bit 3
(G1)
CKI
x
R
Multi-Input
Overflow
Wakeup
Timer0
CKO
(G0)
Bit 2
x
V
LD
LD
CC
Resume Normal
Normal Mode
IDLE Mode
PMC, #00H
Mode
HALT, #01H
EIDLE
Bit 1
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EHALT
Bit 0