ACE1001MT8X Fairchild Semiconductor, ACE1001MT8X Datasheet - Page 21

• Manufacturer Part Number: ACE1001MT8X
• Description: IC MCU 1KBIT EEPROM 8TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: ACEX® 10xxr

Specifications of ACE1001MT8X

• Core Processor: ACE1001
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

ACE1001 Product Family Rev. B.1
6.0 Timer 0
Timer 0 is a 12-bit free running idle timer. Upon power-up or any
reset, the timer is reset to 0x000 and then counts up continuously
based on the instruction clock of 1MHz (1 µs). Software cannot
read from or write to this timer. However, software can monitor the
timer’s pending (T0PND) bit that is set every 8192 cycles (initially
4096 cycles after a reset or after the watchdog has been- ser-
viced). The T0PND flag is set every other time the timer overflows
(transitions from 0xFFF to 0x000). After an overflow, the timer will
reset and restart its counting sequence.
Software can either poll the T0PND bit or vector to an interrupt
subroutine. In order to interrupt on a T0PND, software must be
sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the
Timer 0 control (T0CNTRL) register and also make sure the G bit
is set in SR. Once the timer interrupt is serviced, software should
reset the T0PND bit before exiting the routine. Timer 0 supports
the following functions:
1. Exiting from IDLE mode (See Section 16.0 for details.)
2. Start up delay from HALT mode
3. Watchdog pre-scalar (See Section 7.0 for details.)
The T0INTEN bit is a read/write bit. If set to 0, interrupt requests
from the Timer 0 are ignored. If set to 1, interrupt requests are
accepted. Upon reset, the T0INTEN bit is reset to 0.
The T0PND bit is a read/write bit. If set to 1, it indicates that a Timer
0 interrupt is pending. This bit is set by a Timer 0 overflow and is
reset by software or system reset.
Figure 15: Timer 0 Control Register Definition (T0CNTRL)
Figure 16: Watchdog Server Register (WDSVR)
WKINTEN
Bit 7
Bit 7
0
Bit 6
Bit 6
0
x
Bit 5
Bit 5
x
0
Bit 4
Bit 4
1
x
21
The WKINTEN bit is used in the Multi-input Wakeup/Interrupt
block. See Section 8.0 for details.
7.0 Watchdog
The Watchdog timer is used to reset the device and safely recover
in the rare event of a processor “runaway condition.” The 12-bit
Timer 0 is used as a pre-scalar for Watchdog timer. The Watchdog
timer must be serviced before every 61,440 cycles but no sooner
than 4096 cycles since the last Watchdog reset. The Watchdog is
serviced through software by writing the value 0x1B to the Watch-
dog Service (WDSVR) register (see Figure 16). The part resets
automatically if the Watchdog is serviced too frequent, or not
frequent enough.
The Watchdog timer must be enabled through the Watchdog
enable bit (WDEN) in the initialization register. The WDEN bit can
only be set while the device is in programming mode. Once set, the
Watchdog will always be powered-up enabled. Software cannot
disable the Watchdog. The Watchdog timer can only be disabled
in programming mode by resetting the WDEN bit as long as the
memory write protect (WDIS) feature is not enabled.
WARNING
Ensure that the Watchdog timer has been serviced before enter-
ing IDLE mode because it remains operational during this time.
Bit 3
Bit 3
x
1
Bit 2
Bit 2
x
0
T0PND
Bit 1
Bit 1
1
www.fairchildsemi.com
Bit 0
T0EN
Bit 0
1