ACE1001MT8X Fairchild Semiconductor, ACE1001MT8X Datasheet - Page 23

• Manufacturer Part Number: ACE1001MT8X
• Description: IC MCU 1KBIT EEPROM 8TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: ACEX® 10xxr

Specifications of ACE1001MT8X

• Core Processor: ACE1001
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

ACE1001 Product Family Rev. B.1
Figure 20: I/O Register bit assignments
Table 13: I/O configuration options
9
9.0
The six I/O pins are bi-directional with the exception of G3 which
is always an input with weak pull-up (see Figure 19). The bi-
directional I/O pins can be individually configured by software to
operate as high-impedance inputs, as inputs with weak pull-up, or
as push-pull outputs. The operating state is determined by the
contents of the corresponding bits in the data and configuration
registers. Each bi-directional I/O pin can be used for general
purpose I/O, or in some cases, for a specific alternate function
determined by the on-chip hardware.
9.1 I/O registers
The I/O pins (G0-G5) have three memory-mapped port registers
associated with the I/O circuitry: a port configuration register
Figure 19: PORTGD Logic Diagram
G3 is only an input.
Configuration Bit
Bit 7
I/O Port
x
0
0
1
1
Bit 6
Weak Pull-up Control
x
PORTGC
PORTGD
PORTGP
Bit 5
G5
Data Bit
0
1
0
1
Bit 4
G4
23
High-impedence input (TRI-STATE input)
Input with pull-up (weak one input)
Push-pull zero output
Push-pull one output
(PORTGC), a port data register (PORTGD), and a port input
register (PORTGP). PORTGC is used to configure the pins as
inputs or outputs. A pin may be configured as an input by writing
a 0 or as an output by writing a 1 to its corresponding PORTGC bit.
If a pin is configured as an output, its PORTGD bit represents the
state of the pin (1 = logic high, 0 = logic low). If the pin is configured
as an input, its PORTGD bit selects whether the pin is a weak pull-
up or a high-impedence input. Table 13 provides details of the port
configuration options. The port configuration and data registers
are both read/writable. Reading PORTGP returns the value of the
port pins regardless of how the pins are configured. Since this
device supports multi-input wakeup/interrupt, the PORTG inputs
have Schmitt triggers.
Bit 3
G3
9
Port Pin Configuration
PIN GX
Bit 2
G2
Bit 1
G1
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Bit 0
G0