ACE1001MT8X Fairchild Semiconductor, ACE1001MT8X Datasheet - Page 26

• Manufacturer Part Number: ACE1001MT8X
• Description: IC MCU 1KBIT EEPROM 8TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: ACEX® 10xxr

Specifications of ACE1001MT8X

• Core Processor: ACE1001
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

ACE1001 Product Family Rev. B.1
11.0 Brown-out/Low Battery Detect Circuit
The Brown-out Reset (BOR) and Low Battery Detect (LBD)
circuits on the ACEx microcontroller have been designed to offer
two types of voltage reference comparators. The sections below
will describe the functionality of both circuits.
11.1 Brown Out Reset
The Brown-out Reset (BOR) function is used to hold the device in
reset when V
device is held in its initial condition until V
threshold value. Shortly after V
an internal reset sequence is started. After the reset sequence, the
core fetches the first instruction and starts normal operation.
On the devices, the BOR should be used in situations when V
rises and falls slowly and in situations when V
before rising back to operating range. The BOR can be thought of
as a supplement function to the Power-on Reset when V
fall below ~1.5V. The Power-on Reset circuit works best when V
starts from 0V and rises sharply. So in applications where V
constant, the BOR will give added device stability.
The BOR circuit must be enabled through the BOR enable bit (BOREN)
in the initialization register. The BOREN bit can only be set while the
device is in programming mode. Once set, the BOR will always be
Figure 23: LBD Control Register Definition
Figure 24: BOR/LBD Block Diagram
12
See Figure 13 for information on BLSEL.
Bit 7
CC
drops below a fixed threshold. While in reset, the
Bat_trim[2:0]
Bit 6
Bat_trim[2]
CC
Adjust Reference Voltage
0
0
0
0
1
1
1
1
7
rises above the threshold value,
1.8V
2.2V
Bit 5
6
CC
CC
does not fall to zero
BLSEL
Bat_trim[1]
rises above the
0
1
S
5
12
CC
0
0
1
1
0
0
1
1
Bit 4
does not
CC
4
Vcc
0
is not
CC
CC
3
26
Bat_trim[0]
powered-up enabled. Software cannot disable the BOR. The BOR can
only be disabled in programming mode by resetting the BOREN bit as
long as the global write protect (WDIS) feature is not enabled.
11.2 Low Battery Detect
The Low Battery Detect (LBD) circuit allows software to monitor
the V
programmable voltage reference threshold levels ranging from
2.2V to 3.3V that can be changed on the fly. Once Vcc falls below
the selected threshold, the LBD flag in the LBD control register is
set. The LBD flag will hold its value until V
threshold. (See Figure 23)
The LBD bit is read only. If LBD is 0, it indicates that the V
is higher than the selected threshold. If LBD is 1, it indicates that
the V
can be adjusted up to eight levels using the three trim bits
(Bat_trim[2:0]) of the LBD control register. The LBD flag does not
cause any hardware actions or an interruption of the processor. It
is for software monitoring only.
The LBD function is disabled during HALT/IDLE mode. After
exiting HALT/IDLE, software must wait at lease 10µs before
reading the LBD bit to ensure that the internal circuit has stabi-
lized.
_
+
_
+
BOR
LBD
2
Bit 3
0
1
0
1
0
1
0
1
X
CC
CC
level at the lower voltage ranges. LBD has eight software
level is below the selected threshold. The threshold level
1
0
Bit 2
Threshold
X
Voltage
to RESET logic
Register
Control
3.3
3.1
2.9
2.7
2.5
2.4
2.3
2.2
LBD
Bit 1
X
CC
rises above the
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Bit 0
LBD
CC
level