DSPIC30F3010T-20I/SO Microchip Technology, DSPIC30F3010T-20I/SO Datasheet - Page 90

• Manufacturer Part Number: DSPIC30F3010T-20I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010T-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F3010/3011
14.7
Since the QEI module can function as a quadrature
encoder interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.
14.7.1
When the CPU is placed in the Idle mode, the QEI
module
(QEICON<13>) = 0. This bit defaults to a logic ‘0’
upon executing POR and BOR. For halting the QEI
module during the CPU Idle mode, QEISIDL should
be set to ‘1’.
14.7.2
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit
(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU Idle mode had not been
entered.
DS70141B-page 88
timer
QEI Module Operation During CPU
Idle Mode
will
QEI OPERATION DURING CPU IDLE
MODE
TIMER OPERATION DURING CPU
IDLE MODE
will
operate
operate
if
if
the
the
QEISIDL
QEISIDL
Preliminary
bit
bit
14.8
The quadrature encoder interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
• Detection of qualified index pulse, or if CNTERR
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 status register.
Enabling an interrupt is accomplished via the respec-
tive Enable bit, QEIIE. The QEIIE bit is located in the
IEC2 control register.
rollover/underflow
bit is set
Quadrature Encoder Interface
Interrupts
© 2005 Microchip Technology Inc.