DSPIC30F3010T-20I/SO Microchip Technology, DSPIC30F3010T-20I/SO Datasheet - Page 63

IC DSPIC MCU/DSP 24K 28SOIC

DSPIC30F3010T-20I/SO

Manufacturer Part Number
DSPIC30F3010T-20I/SO
Description
IC DSPIC MCU/DSP 24K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3010T-20I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.3
The Input Change Notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a change-of-
state on selected input pins. This module is capable of
detecting input change-of-states even in Sleep mode,
when the clocks are disabled. There are 10 external
signals (CN0 through CN7, CN17 and CN18) that may
be selected (enabled) for generating an interrupt
request on a change-of-state.
Please refer to the Pin Diagrams for CN pin locations.
TABLE 8-3:
© 2005 Microchip Technology Inc.
CNEN1
CNPU1
Legend:
Note 1:
SFR Name
Input Change Notification Module
u = uninitialized bit; — = unimplemented bit
Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit posi-
tions, are available on this device.
Addr.
00C0
00C4
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0)
CN7PUE
CN7IE
Bit 7
CN6PUE
CN6IE
Bit 6
CN5PUE
CN5IE
Bit 5
CN4PUE
CN4IE
Bit 4
Preliminary
CN3PUE
CN3IE
Bit 3
CN2PUE
dsPIC30F3010/3011
CN2IE
Bit 2
CN1PUE
CN1IE
Bit 1
CN0PUE
CN0IE
Bit 0
0000 0000 0000 0000
0000 0000 0000 0000
DS70141B-page 61
Reset State

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