AT90CAN128-16AJ Atmel, AT90CAN128-16AJ Datasheet - Page 179
![IC MCU AVR FLASH 128K 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT90CAN128-16AJ
Manufacturer Part Number
AT90CAN128-16AJ
Description
IC MCU AVR FLASH 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16AJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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17.4
17.4.1
7679H–CAN–08/08
Clock Generation
Internal Clock Generation – Baud Rate Generator
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USARTn
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 17-2
Figure 17-2. USARTn Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USARTn Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(
when the UBRRnL Register is written. A clock is generated each time the counter reaches zero.
This clock is the baud rate generator clock output (=
the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator
output is used directly by the Receiver’s clock and data recovery units. However, the recovery
f
clk
io
), is loaded with the UBRRn value each time the counter has counted down to zero or
txn clk
rxn clk
xn cki
xn cko
f
clk
DDR_XCKn
XCKn
io
Pin
shows a block diagram of the clock generation logic.
xn cko
xn cki
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
System I/O Clock frequency.
clk
Down-Counter
io
Prescaling
Register
UBRRn
Sync
UBRRn+1
f
clk
UCPOLn
Detector
io
Edge
/2
Figure
f
clk
io
17-2.
/(UBRRn+1)). The Transmitter divides
/4
AT90CAN32/64/128
/2
DDR_XCKn
U2Xn
0
1
0
1
0
1
1
0
UMSELn
txn clk
rxn clk
179
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