AT90CAN128-16AJ Atmel, AT90CAN128-16AJ Datasheet - Page 177

• Manufacturer Part Number: AT90CAN128-16AJ
• Description: IC MCU AVR FLASH 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-16AJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

17. USART (USART0 and USART1)
17.1
17.2
17.3
7679H–CAN–08/08
Features
Overview
Dual USART
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The main features are:
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Many registers and bit references in this section are written in general form.
The AT90CAN32/64/128 has two USART’s, USART0 and USART1. The functionality for both
USART’s is described below. USART0 and USART1 have different I/O registers as shown in
“Register Summary” on page
A simplified block diagram of the USARTn Transmitter is shown in
I/O Registers and I/O pins are shown in bold.
• A lower case “n” replaces the USART number, in this case 0 or 1. However, when using the
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
register or bit defines in a program, the precise form must be used, i.e., UDR0 for accessing
USART0 I/O data value and so on.
405.
AT90CAN32/64/128
Figure
17-1. CPU accessible
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