AT89C5132-ROTIL Atmel, AT89C5132-ROTIL Datasheet - Page 74

• Manufacturer Part Number: AT89C5132-ROTIL
• Description: IC 8051 MCU FLASH 64K USB 80TQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5132-ROTIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
• Peripherals: I²S, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

74
AT89C5132
Reset Value = 0000 0000b
Table 58. USBINT Register
USBINT (S:BDh) – USB Global Interrupt Register
Reset Value = 0000 0000b
Table 59. USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
Number
Number
7 - 6
2 - 1
Bit
5
4
3
0
6-0
7
Bit
-
7
7
-
Mnemonic Description
WUPCPU
EORINT
SOFINT
SPINT
Mnemonic Description
Bit
UADD6:0
-
-
6
-
FEN
Bit
6
-
Reserved
The values read from these Bits are always 0. Do not set these Bits.
Wake Up CPU Interrupt Flag
Set by hardware when the USB controller is in SUSPEND state and is re-activated
by a non-idle signal from USB line (not by an upstream resume). This triggers a USB
interrupt when EWUPCPU is set in the USBIEN.
Cleared by software after re-enabling all USB clocks.
End of Reset Interrupt Flag
Set by hardware when a End of Reset has been detected by the USB controller. This
triggers a USB interrupt when EEORINT is set in USBIEN.
Cleared by software.
Start of Frame Interrupt Flag
Set by hardware when a USB Start of Frame packet (SOF) has been properly
received. This triggers a USB interrupt when ESOFINT is set in USBIEN.
Cleared by software.
Reserved
The values read from these Bits are always 0. Do not set these Bits.
Suspend Interrupt Flag
Set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for
3 ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN.
Cleared by software.
WUPCPU
Function Enable Bit
Set to enable the function. The device firmware shall set this bit after it has
received a USB reset and participate in the following configuration process with
the default address (FEN is reset to 0).
Cleared by hardware at power-up, should not be cleared by the device firmware
once set.
USB Address Bits
This field contains the default address (0) after power-up or USB bus reset.
It shall be written with the value set by a SET_ADDRESS request received by
the device firmware.
EWUPCPU
5
5
EORINT
EEORINT
4
4
SOFINT
ESOFINT
3
3
2
-
2
-
1
-
1
-
4173E–USB–09/07
ESPINT
SPINT
0
0