AT89C5132-ROTIL Atmel, AT89C5132-ROTIL Datasheet - Page 132

• Manufacturer Part Number: AT89C5132-ROTIL
• Description: IC 8051 MCU FLASH 64K USB 80TQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5132-ROTIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
• Peripherals: I²S, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 20-2. Complete Data Transfer on TWI Bus
20.1.1
132
AT89C5132
Bit Rate
SDA
SCL
S
The four operating modes are:
•
•
•
•
Data transfer in each mode of operation are shown in Figure 20-3 through Figure 20-6. These
figures contain the following abbreviations:
A
A
Data
S
P
MR
MT
SLA
GCA
R
W
In Figure 20-3 through Figure 20-6, circles are used to indicate when the serial interrupt flag is
set. The numbers in the circles show the status code held in SSSTA. At these points, a service
routine must be executed to continue or complete the serial transfer. These service routines are
not critical since the serial transfer is suspended until the serial interrupt flag is cleared by
software.
When the serial interrupt routine is entered, the status code in SSSTA is used to branch to the
appropriate service routine. For each status code, the required software action and details of the
following serial transfer are given in Table 20 through Table 20-6.
The bit rate can be selected from seven predefined bit rates or from a programmable bit rate
generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 26). The
predefined bit rates are derived from the peripheral clock (F
block as detailed in Section "Oscillator", page 12, while bit rate generator is based on timer 1
overflow output.
MSB
1
Master transmitter
Master receiver
Slave transmitter
Slave receiver
Slave Address
2
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level on SDA)
8-bit data Byte
START condition
STOP condition
Master Receive
Master Transmit
Slave Address
General Call Address (00h)
Read bit (high level at SDA)
Write bit (low level at SDA)
direction
R/W
bit
8
receiver
signal
ACK
from
9
Clock Line Held Low While Serial Interrupts Are Serviced
1
Nth data Byte
2
PER
) issued from the Clock Controller
8
receiver
signal
ACK
from
9
P/S
4173E–USB–09/07