AT89C5132-ROTIL Atmel, AT89C5132-ROTIL Datasheet - Page 27
![IC 8051 MCU FLASH 64K USB 80TQFP](/photos/12/13/121358/313-80-tqfp_sml.jpg)
AT89C5132-ROTIL
Manufacturer Part Number
AT89C5132-ROTIL
Description
IC 8051 MCU FLASH 64K USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Datasheets
1.AT89C5132-ROTUL.pdf
(182 pages)
2.AT89C5132-ROTUL.pdf
(38 pages)
3.AT89C5132-ROTIL.pdf
(33 pages)
Specifications of AT89C5132-ROTIL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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8.4
4173E–USB–09/07
Registers
Table 13. PSW Register
PSW (S:8Eh) – Program Status Word Register
Reset Value = 0000 0000b
Table 14. AUXR Register
AUXR (S:8Eh) – Auxiliary Control Register
Bit Number
Bit Number
4 - 3
3 - 2
CY
7
6
5
4
7
7
6
5
2
1
0
7
-
Mnemonic
Mnemonic
DPHDIS
XRS1:0
EXT16
EXT16
RS1:0
AC
CY
AC
OV
Bit
M0
Bit
F0
F1
P
6
6
-
Description
Carry Flag
Carry out from bit 1 of ALU operands.
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
User Definable Flag 0.
Register Bank Select Bits
Refer to Table 10 for Bits description.
Overflow Flag
Overflow set by arithmetic operations.
User Definable Flag 1
Parity Bit
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
Description
Reserved
The values read from this bit is indeterminate. Do not set this bit.
External 16-bit Access Enable Bit
Set to enable 16-bit access mode during MOVX instructions.
Clear to disable 16-bit access mode and enable standard 8-bit access mode during
MOVX instructions.
External Memory Access Stretch Bit
Set to stretch RD or WR signals duration to 15 CPU clock periods.
Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
DPH Disable Bit
Set to disable DPH output on P2 when executing MOVX @DPTR instruction.
Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.
Expanded RAM Size Bits
Refer to Table 11 for ERAM size description.
M0
F0
5
5
DPHDIS
RS1
4
4
XRS1
RS0
3
3
XRS0
OV
2
2
EXTRAM
AT89C5132
F1
1
1
AO
P
0
0
27
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