AT89C5132-ROTIL Atmel, AT89C5132-ROTIL Datasheet - Page 121
![IC 8051 MCU FLASH 64K USB 80TQFP](/photos/12/13/121358/313-80-tqfp_sml.jpg)
AT89C5132-ROTIL
Manufacturer Part Number
AT89C5132-ROTIL
Description
IC 8051 MCU FLASH 64K USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Datasheets
1.AT89C5132-ROTUL.pdf
(182 pages)
2.AT89C5132-ROTUL.pdf
(38 pages)
3.AT89C5132-ROTIL.pdf
(33 pages)
Specifications of AT89C5132-ROTIL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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19.1
19.1.1
Figure 19-3. SPI Master Mode Block Diagram
Note:
19.1.2
4173E–USB–09/07
Description
MSTR bit in SPCON is set to select master mode.
Master Mode
Slave Mode
CLOCK
PER
MOSI/P4.1
MISO/P4.0
SCK/P4.2
SPCON.6
SS/P4.3
SPEN
The SPI controller interfaces with the C51 core through three special function registers: SPCON,
the SPI control register (see Table 98); SPSTA, the SPI status register (see Table 99); and
SPDAT, the SPI data register (see Table 100).
The SPI operates in master mode when the MSTR bit in SPCON is set.
Figure 19-3 shows the SPI block diagram in master mode. Only a master SPI module can initiate
transmissions. Software begins the transmission by writing to SPDAT. Writing to SPDAT writes
to the shift register while reading SPDAT reads an intermediate register updated at the end of
each transfer.
The byte begins shifting out on the MOSI pin under the control of the bit rate generator. This
generator also controls the shift register of the slave peripheral through the SCK output pin. As
the byte shifts out, another byte shifts in from the slave peripheral on the MISO pin. The byte is
transmitted most significant bit (MSB) first. The end of transfer is signalled by SPIF being set.
In case of the AT89C5132 is the only master on the bus, it can be useful not to use SS pin and
get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been
loaded in SPDAT.
Figure 19-4 shows the SPI block diagram in slave mode. In slave mode, before data transmis-
sion occurs, the SS pin of the slave SPI must be asserted to low level. SS must remain low until
the transmission of the byte is complete. In the slave SPI module, data enters the shift register
through the MOSI pin under the control of the serial clock provided by the master SPI module on
the SCK input pin. When the master starts a transmission, the data in the shift register begins
shifting out on the MISO pin. The end of transfer is signaled by SPIF being set.
Bit Rate Generator
SPR2:0
SPCON.5
SPCON
SSDIS
Control and Clock Logic
SPCON.2
CPHA
SPCON.3
CPOL
I
SPSTA.4
SPSTA.6
SPSTA.7
MODF
WCOL
SPIF
8-bit Shift Register
SPDAT RD
SPDAT WR
AT89C5132
Q
121
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