DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 9

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

7. Module: CPU
8. Module: Timer
© 2010 Microchip Technology Inc.
The DISI instruction will not disable interrupts
when a DISI instruction is executed in the same
instruction
decrements to zero. For example, when user code
executes a DISI #7, interrupts for 7 + 1 cycles
(7 + the DISI instruction itself) are disabled. In
that case, the DISI instruction uses a counter that
counts down from 7 to 0. The counter is loaded
with 7 at the end of the DISI instruction.
If the user code executes another DISI on the
instruction cycle where the DISI counter has
become zero, the new DISI count is loaded, but
the DISI state machine does not properly re-
engage and continues to disable interrupts. At this
point, all interrupts are enabled. The next time the
user code executes a DISI instruction, the feature
will act normally and block interrupts.
To summarize, it is only when a DISI execution is
coincident with the current DISI count = 0, that the
issue occurs. Executing a DISI instruction before
the DISI counter reaches zero will not produce
this error. In this case, the DISI counter is loaded
with the new value, and interrupts remain disabled
until the counter becomes zero.
Work around
When executing multiple DISI instructions within
the source code, make sure that subsequent
DISI instructions have at least one instruction
cycle between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, ensure that the subsequent DISI
instructions are called before the DISI counter
decrements to zero.
Affected Silicon Revisions
Pairs of 16-bit timers may be combined to form
32-bit timers. For example, Timer2 and Timer3 are
combined into a single 32-bit timer. For this
release of silicon, when a 32-bit timer is prescaled
by ratios other than 1:1, unexpected results may
occur.
Work around
None. The application may only use the 1:1
prescaler for 32-bit timers.
Affected Silicon Revisions
A0
A0
X
X
A1
A1
X
X
cycle
A2
A2
X
X
A3
A3
X
X
that
A4
A4
X
X
the
DISI
counter
9. Module: Output Compare
10. Module: Output Compare
If the desired duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
The second problem is that on the next cycle after
the glitch, the OC pin does not go high, or in other
words, it misses the next compare for any value
written on OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
Affected Silicon Revisions
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The Output Compare module is configured and
When these events occur, the Output Compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a timer
interrupt, and write to the associated PORT
register to control the pin manually.
Affected Silicon Revisions
A0
A0
high using the Output Compare module or a
write to the associated PORT register.
enabled to drive the pin low at some later time
(OCxCON = Ox0002 or OCxCON = 0x0003).
X
X
register when operating in PWM mode. In this
case, no 0% duty cycle is achievable.
Output Compare module can be disabled for
0% duty cycles, and re-enabled for non-zero
percent duty cycles.
CY
A1
A1
X
X
) after the module is enabled.
dsPIC30F2010
A2
A2
X
X
A3
A3
X
X
A4
A4
X
X
DS80451E-page 9
CY
.