DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

TABLE 2:
© 2010 Microchip Technology Inc.
Operations
Note 1:
Program
Memory
Module
Sleep
Mode
Timer
I
PWM
Flash
FRC
PSV
2
PLL
QEI
SPI
I
I
I
I
I/O
C™
2
2
2
2
C
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Bus Collision
Debug Mode
Slave Mode
Sleep Mode
Lock Status
Generation
Multiplexed
Addressing
Addressing
Addressing
Operation
Feature
Interrupt
with IC1
SILICON ISSUE SUMMARY (CONTINUED)
Port Pin
RTSP
10-bit
Mode
10-bit
Mode
10-bit
Mode
bit
—
—
—
—
Number
Item
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
When enabled, the SPI module does not disable RF2 as
a general I/O pin.
The Quadrature Encoder Interface (QEI) module does
not generate an interrupt in a particular overflow
condition.
Execution of the Sleep instruction (PWRSAV #0) may
cause incorrect program operation after the device
wakes up from Sleep. The current consumption during
Sleep may also increase beyond the specifications
listed in the device data sheet.
The I
operating as an I
PTMR does not continue counting down after halting
code execution in Debug mode.
The Port I/O pin multiplexed with the Input Capture 1
(IC1) function cannot be used as a digital input pin when
the UART auto-baud feature is enabled.
Internal FRC accuracy does not perform to
specification.
When the I
using the same address bits (A10 and A9) as other I
devices, the A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up
from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an oscillator
failure trap even when the PLL is still locked and
functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any PSV
page.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least
Significant bits (LSbs) of the address are the same as
the 7-bit reserved addresses.
When the I
with an address of 0x102, the I2CxRCV register content
for the lower address byte is 0x01 rather than 0x02.
When the I
device generates a glitch on the SDA and SCL pins,
causing a false communication start in a single-master
configuration or a bus collision in a multi-master
configuration.
Run-Time Self-Programming (RTSP) operations need to
be timed by the application software. Self-timed write
operations are not supported.
2
C module loses incoming data bytes when
2
2
2
C module is configured for 10-bit addressing
C module is configured as a 10-bit slave
C module is enabled, the dsPIC
2
C slave.
Issue Summary
dsPIC30F2010
®
DSC
2
C
A0 A1 A2 A3 A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Revisions
DS80451E-page 3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X