DSPIC30F2010-30I/SO Microchip Technology, DSPIC30F2010-30I/SO Datasheet - Page 11

• Manufacturer Part Number: DSPIC30F2010-30I/SO
• Description: IC DSPIC MCU/DSP 12K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

15. Module: Interrupt Controller
EXAMPLE 9:
EXAMPLE 11:
© 2010 Microchip Technology Inc.
.include "p30fxxxx.inc"
...
DISI #4 ; protect the disable
; of INT1
BCLR IEC1, #INT1IE ; disable interrupt 1
... ; next instruction
; protected by DISI
// Note: Macros defined in device include files
#define SET_AND_SAVE_CPU_IPL (save_to, ipl){ \
save_to = SRbits.IPL; \
SET_CPU_IPL (ipl); } (void) 0;
#define RESTORE_CPU_IPL (saved_to) SET_CPU_IPL (saved_to)
#include "p30fxxxx.h"
. . .
int save_to;
SET_AND_SAVE_CPU_IPL (save_to, 3)
. . .
RESTORE_CPU_IPL (save_to)
The following sequence of events will lead to an
address error trap. The generic term “Interrupt 1”
is used to represent any enabled dsPIC30F
interrupt.
1. User software performs one of the following
2. Interrupt 1 occurs between 2 and 4 instruction
Work arounds
Work around 1: For Assembly Language
Source Code
The user may disable interrupt nesting, disable
interrupts before modifying the Interrupt 1 setting,
or execute a DISI instruction before modifying the
CPU IPL or Interrupt 1. A minimum DISI value of 4
is required if the DISI instruction is executed
immediately before the CPU IPL or Interrupt 1 is
modified, as shown in
to have DISI active for four cycles after the CPU
IPL or Interrupt 1 is modified.
operations:
-
-
-
-
cycles after any of the operations listed above.
CPU IPL is raised to Interrupt 1 IPL
level or higher, or
Interrupt 1 IPL is lowered to CPU IPL
level or lower, or
Interrupt 1 is disabled (Interrupt 1 IE
bit set to ‘0’), or
Interrupt 1 flag is cleared.
USING DISI
USING SET_AND_SAVE_CPU_IPL AND RESTORE_CPU_IPL MACROS
Example
9. It is necessary
EXAMPLE 10:
// Note: Macro defined in device include
// files
#define SET_CPU_IPL (ipl){ \
int DISI_save; \
\
DISI_save = DISICNT; \
asm volatile ("disi #0x3FFF");\
SRbits.IPL = ipl; \
__builtin_nop();
__builtin_nop();
DISICNT = DISI_save; } (void) 0;
#include "p30fxxxx.h"
. . .
SET_CPU_IPL (3)
. . .
Work around 2: For C Language Source Code
For applications using the C language, MPLAB C
Compiler for dsPIC DSCs versions 1.32 and
higher, provide several macros for modifying the
CPU IPL. The SET_CPU_IPL macro provides the
ability to safely modify the CPU IPL, as shown in
Example
There is one level of DISI, so this macro saves and
restores the DISI state. For temporarily modifying
and
SET_AND_SAVE_CPU_IPL
RESTORE_CPU_IPL can be used, as shown in
Example
SET_CPU_IPL macro.
restoring
10.
11. These macros also make use of the
dsPIC30F2010
USING SET_CPU_IPL
MACRO
the
\
\
CPU
IPL,
DS80451E-page 11
the
macros
and