ATMEGA169V-8MI Atmel, ATMEGA169V-8MI Datasheet - Page 30
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ATMEGA169V-8MI
Manufacturer Part Number
ATMEGA169V-8MI
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA169V-1MI
ATMEGA169V-1MI
ATMEGA169V-1MI
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Clock Prescale Register –
CLKPR
30
ATmega169/V
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here,
T1 is the previous clock period, and T2 is the period corresponding to the new prescaler
setting.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other
2. Within four cycles, write the desired value to CLKPS while writing a zero to
Interrupts must be disabled when changing prescaler setting to make sure the write pro-
cedure is not interrupted.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKPCE bit.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The divi-
sion factors are given in Table 13.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-
grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits
are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if
the selected clock source has a higher frequency than the maximum frequency of the
device at the present operating conditions. Note that any value can be written to the
CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating condi-
tions. The device is shipped with the CKDIV8 Fuse programmed.
Bit
Read/Write
Initial Value
bitsin CLKPR to zero.
CLKPCE.
CLKPCE
R/W
7
0
R
6
–
0
R
5
–
0
R
4
–
0
CLKPS3
R/W
3
CLKPS2
See Bit Description
R/W
2
CLKPS1
R/W
1
CLKPS0
R/W
0
2514P–AVR–07/06
CLKPR
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