ATMEGA169V-8MI Atmel, ATMEGA169V-8MI Datasheet - Page 287
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ATMEGA169V-8MI
Manufacturer Part Number
ATMEGA169V-8MI
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA169V-1MI
ATMEGA169V-1MI
ATMEGA169V-1MI
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PROG_COMMANDS (0x5)
PROG_PAGELOAD (0x6)
PROG_PAGEREAD (0x7)
Data Registers
2514P–AVR–07/06
The AVR specific public JTAG instruction for entering programming commands via the
JTAG port. The 15-bit Programming Command Register is selected as Data Register.
The active states are the following:
•
•
•
•
The AVR specific public JTAG instruction to directly load the Flash data page via the
JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is
physically the 8 LSBs of the Programming Command Register. The active states are the
following:
•
•
The AVR specific public JTAG instruction to directly capture the Flash content via the
JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is
physically the 8 LSBs of the Programming Command Register. The active states are the
following:
•
•
The Data Registers are selected by the JTAG instruction registers described in section
“Programming Specific JTAG Instructions” on page 285. The Data Registers relevant for
programming operations are:
•
•
•
•
Capture-DR: The result of the previous command is loaded into the Data Register.
Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the
previous command and shifting in the new command.
Update-DR: The programming command is applied to the Flash inputs
Run-Test/Idle: One clock cycle is generated, executing the applied command (not
always required, see Table 131 below).
Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
Update-DR: The content of the Flash Data Byte Register is copied into a temporary
register. A write sequence is initiated that within 11 TCK cycles loads the content of
the temporary register into the Flash page buffer. The AVR automatically alternates
between writing the low and the high byte for each new Update-DR state, starting
with the low byte for the first Update-DR encountered after entering the
PROG_PAGELOAD command. The Program Counter is pre-incremented before
writing the low byte, except for the first written byte. This ensures that the first data is
written to the address set up by PROG_COMMANDS, and loading the last location
in the page buffer does not make the program counter increment into the next page.
Capture-DR: The content of the selected Flash byte is captured into the Flash Data
Byte Register. The AVR automatically alternates between reading the low and the
high byte for each new Capture-DR state, starting with the low byte for the first
Capture-DR encountered after entering the PROG_PAGEREAD command. The
Program Counter is post-incremented after reading each high byte, including the
first read byte. This ensures that the first data is captured from the first address set
up by PROG_COMMANDS, and reading the last location in the page makes the
program counter increment into the next page.
Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
Reset Register
Programming Enable Register
Programming Command Register
Flash Data Byte Register
ATmega169/V
287
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