ATMEGA169V-8MI Atmel, ATMEGA169V-8MI Datasheet - Page 212
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATMEGA169V-8MI
Manufacturer Part Number
ATMEGA169V-8MI
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA169V-1MI
ATMEGA169V-1MI
ATMEGA169V-1MI
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LCD Contrast
Controller/Power Supply
LCDCAP
LCD Buffer Driver
Mode of Operation
Static Duty and Bias
212
ATmega169/V
Addressing COM0 starts a frame by driving opposite phase with large amplitude out on
COM0 compared to none addressed COM lines. Non-energized segments are in phase
with the addressed COM0, and energized segments have opposite phase and large
amplitude. For waveform figures refer to “Mode of Operation” on page 212. Latched
data from LCDDR4 - LCDDR0 is multiplexed into the decoder. The decoder is controlled
from the LCD timing and sets up signals controlling the analog switches to produce an
output waveform. Next, COM1 is addressed, and latched data from LCDDR9 - LCDDR5
is input to decoder. Addressing continuous until all COM lines are addressed according
to number of common (duty). The display data are latched before a new frame start.
The peak value (V
controlled by software from 2.6V to 3.35V independent of V
output to the LCD until V
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as
shown in Figure 98. This capacitor acts as a reservoir for LCD power (V
capacitance reduces ripple on V
value.
Figure 98. LCDCAP Connection
Intermediate voltage levels are generated from buffers/drivers. The buffers are active
the amount of time specified by LCDDC[2:0] in “LCD Contrast Control Register – LCD-
CCR” on page 223. Then LCD output pins are tri-stated and buffers are switched off.
Shortening the drive time will reduce power consumption, but displays with high internal
resistance or capacitance may need longer drive time to achieve sufficient contrast.
If all segments on a LCD have one electrode common, then each segment must have a
unique terminal.
This kind of display is driven with the waveform shown in Figure 99. SEG0 - COM0 is
the voltage across a segment that is on, and SEG1 - COM0 is the voltage across a seg-
ment that is off.
LCD
) on the output waveform determines the LCD Contrast. V
LCD
has reached its target value.
LCD
62
63
64
but increases the time until VLCD reaches its target
1
2
3
CC
. An internal signal inhibits
2514P–AVR–07/06
LCD
). A large
LCD
is
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