ATMEGA169V-8MI Atmel, ATMEGA169V-8MI Datasheet - Page 217
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ATMEGA169V-8MI
Manufacturer Part Number
ATMEGA169V-8MI
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA169V-1MI
ATMEGA169V-1MI
ATMEGA169V-1MI
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Updating the LCD
2514P–AVR–07/06
Note:
Before a re-initialization is done, the LCD controller/driver should be disabled
Display memory (LCDDR0, LCDDR1, ..), LCD Blanking (LCDBL), Low power waveform
(LCDAB) and contrast control (LCDCCR) are latched prior to every new frame. There
are no restrictions on writing these LCD Register locations, but an LCD data update may
be split between two frames if data are latched while an update is in progress. To avoid
this, an interrupt routine can be used to update Display memory, LCD Blanking, Low
power waveform, and contrast control, just after data are latched.
Assembly Code Example
C Code Example
LCD_Init:
Void LCD_Init(void);
{
}
; Use 32 kHz crystal oscillator
; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins
ldi
sts
; Using 16 as prescaler selection and 7 as LCD Clock Divide
; gives a frame rate of 49 Hz
ldi
sts
; Set segment drive time to 125 µs and output voltage to 3.3 V
ldi
sts
; Enable LCD, default waveform and no interrupt enabled
ldi
sts
ret
/* Use 32 kHz crystal oscillator */
/* 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins */
LCDCRB = (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2);
/* Using 16 as prescaler selection and 7 as LCD Clock Divide */
/* gives a frame rate of 49 Hz */
LCDFRR = (1<<LCDCD2) | (1<<LCDCD1);
/* Set segment drive time to 125 µs and output voltage to 3.3 V*/
LCDCCR = (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1);
/* Enable LCD, default waveform and no interrupt enabled */
LCDCRA = (1<<LCDEN);
1. See “About Code Examples” on page 6.
r16, (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2)
LCDCRB, r16
r16, (1<<LCDCD2) | (1<<LCDCD1)
LCDFRR, r16
r16, (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1)
LCDCCR, r16
r16, (1<<LCDEN)
LCDCRA, r16
(1)
(1)
ATmega169/V
217
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