ATMEGA162L-8MI Atmel, ATMEGA162L-8MI Datasheet - Page 243

• Manufacturer Part Number: ATMEGA162L-8MI
• Description: IC MCU AVR 16K 3V 8MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

SPI Serial Programming
Algorithm
2513C–AVR–09/02
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
High:> 2 CPU clock cycles for f
When writing serial data to the ATmega162, data is clocked on the rising edge of SCK.
When reading data from the ATmega162, data is clocked on the falling edge of SCK.
See Figure 106.
To program and verify the ATmega162 in the SPI Serial Programming mode, the follow-
ing sequence is recommended (See four byte instruction formats in Table 111 ):
1. Power-up sequence:
2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Pro-
3. The SPI Serial Programming instructions will not work if the communication is
4. The Flash is programmed one page at a time. The memory page is loaded one
5. The EEPROM array can either be programmed one page at a time or it can be
For Page Programming, the following algorithm is used:
Alteratively, the EEPROM can be programmed bytewise
Apply power between V
some systems, the programmer can not guarantee that SCK is held low during
Power-up. In this case, RESET must be given a positive pulse of at least two
CPU clock cycles duration after SCK has been set to “0”.
gramming Enable serial instruction to pin MOSI.
out of synchronization. When in sync. the second byte (0x53), will echo back
when issuing the third byte of the Programming Enable instruction. Whether the
echo is correct or not, all four bytes of the instruction must be transmitted. If the
0x53 did not echo back, give RESET a positive pulse and issue a new Program-
ming Enable command.
byte at a time by supplying the 6 LSB of the address and data together with the
Load Program Memory Page instruction. To ensure correct loading of the page,
the data low byte must be loaded before data high byte is applied for a given
address. The Program Memory Page is stored by loading the Write Program
Memory Page instruction with the 8 MSB of the address. If polling is not used,
the user must wait at least t
110.) Accessing the SPI serial programming interface before the Flash write
operation completes can result in incorrect programming.
programmed byte by byte.
The EEPROM memory page is loaded one byte at a time by supplying the 2 LSB of
the address and data together with the Load EEPROM Memory Page instruction.
The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page
instruction with the 8 MSB of the address. If polling is not used, the user must wait at
least t
Serial Programming interface before the EEPROM write operation completes can
result in incorrect programming.
The EEPROM array is programmed one byte at a time by supplying the address
and data together with the Write EEPROM instruction. An EEPROM memory loca-
tion is first automatically erased before new data is written. If polling is not used, the
user must wait at least t
a chip erased device, no 0xFFs in the data file(s) need to be programmed.
WD_EEPROM
before issuing the next page. (See Table 100.) Accessing the SPI
CC
WD_EEPROM
ck
and GND while RESET and SCK are set to “0”. In
ck
WD_FLASH
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
before issuing the next byte. (See Table 110.) In
before issuing the next page. (See Table
ATmega162(V/U/L)
ck
ck
>= 12 MHz
>= 12 MHz
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