ATMEGA162-16PC Atmel, ATMEGA162-16PC Datasheet - Page 127

• Manufacturer Part Number: ATMEGA162-16PC
• Description: IC MCU AVR 16K 5V 16MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

2513C–AVR–09/02
Table 54 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the
fast PWM mode.
Table 54. Compare Output Mode, Fast PWM
Note:
Table 55 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the
phase correct or the phase and frequency correct, PWM mode.
Table 55. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
Note:
• Bit 3 – FOCnA: Force Output Compare for channel A
• Bit 2 – FOCnB: Force Output Compare for channel B
The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to
zero when TCCRnA is written when operating in a PWM mode. When writing a logical
one to the FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform
Generation unit. The OCnA/OCnB output is changed according to its COMnx1:0 bits
setting. Note that the FOCnA/FOCnB bits are implemented as strobes. Therefore it is
the value present in the COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB bits are always read as zero.
COMnA1/
COMnA1/
COMnB1
COMnB1
(1)
0
0
1
1
0
0
1
1
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is
set. In this case the compare match is ignored, but the set or clear is done at TOP.
See “Fast PWM Mode” on page 118. for more details.
set. See “Phase Correct PWM Mode” on page 120. for more details.
COMnA0
COMnB0
COMnA0/
COMnB0
0
1
0
1
0
1
0
1
Description
Normal port operation, OCnA/OCnB disconnected.
WGMn3=0: Normal port operation, OCnA/OCnB disconnected.
WGMn3=1: Toggle OCnA on compare match, OCnB reserved.
Clear OCnA/OCnB on compare match when up-counting. Set
OCnA/OCnB on compare match when downcounting.
Set OCnA/OCnB on compare match when up-counting. Clear
OCnA/OCnB on compare match when downcounting.
Description
Normal port operation, OCnA/OCnB disconnected.
WGMn3=0: Normal port operation, OCnA/OCnB disconnected.
WGMn3=1: Toggle OCnA on compare match, OCnB reserved.
Clear OCnA/OCnB on compare match, set OCnA/OCnB at TOP.
Set OCnA/OCnB on compare match, clear OCnA/OCnB at TOP.
(1)
ATmega162(V/U/L)
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