PIC16C925/CL Microchip Technology, PIC16C925/CL Datasheet - Page 93

• Manufacturer Part Number: PIC16C925/CL
• Description: IC MCU EPROM 4KX14 LCDDVR 68CLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C925/CL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: EPROM
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-CLCC Window, 68-CERQUAD
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA16XL680 - ADAPTER DEVICE FOR MPLAB-ICEAC164024 - ADAPTER PICSTART PLUS 68PLCCAC164022 - MODULE SKT PROMATEII 68PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.2
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver, such as a Microchip AY0438,
can be synchronized for segment data update to the
LCD frame.
FIGURE 11-7:
2001 Microchip Technology Inc.
COM0
COM1
COM2
COM3
T
T
LCD Interrupts
FWR
FINT
Frame
Boundary
= T
= (T
(T
FRAME
FWR
FWR
EXAMPLE WAVEFORMS AND INTERRUPT TIMING
IN QUARTER-DUTY CYCLE DRIVE
/(LMUX1:LMUX0 + 1) + T
/2 - (2T
/2 - (1T
CY
CY
+ 40 ns))
+ 40 ns))
1 Frame
minimum = 1.5(T
maximum = 1.5(T
CY
Preliminary
/2
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(T
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (T
must be written within T
controller will begin to access the data for the next
frame.
LCD
Interrupt
Occurs
FINT
FRAME
FRAME
), as shown in Figure 11-7. The LCD controller
T
FWR
/4) - (2T
/4) - (1T
T
FINT
PIC16C925/926
CY
CY
Controller Accesses
Next Frame Data
+ 40 ns)
+ 40ns)
Frame
Boundary
FWR
, as this is when the LCD
DS39544A-page 91
FWR
). New data
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V